//megafunction wizard: %Altera SOPC Builder%
//GENERATION: STANDARD
//VERSION: WM1.0


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// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module AREA_s1_arbitrator (
                            // inputs:
                             AREA_s1_readdata,
                             clk,
                             cpu_data_master_address_to_slave,
                             cpu_data_master_read,
                             cpu_data_master_write,
                             reset_n,

                            // outputs:
                             AREA_s1_address,
                             AREA_s1_readdata_from_sa,
                             AREA_s1_reset_n,
                             cpu_data_master_granted_AREA_s1,
                             cpu_data_master_qualified_request_AREA_s1,
                             cpu_data_master_read_data_valid_AREA_s1,
                             cpu_data_master_requests_AREA_s1,
                             d1_AREA_s1_end_xfer
                          )
;

  output  [  1: 0] AREA_s1_address;
  output  [ 31: 0] AREA_s1_readdata_from_sa;
  output           AREA_s1_reset_n;
  output           cpu_data_master_granted_AREA_s1;
  output           cpu_data_master_qualified_request_AREA_s1;
  output           cpu_data_master_read_data_valid_AREA_s1;
  output           cpu_data_master_requests_AREA_s1;
  output           d1_AREA_s1_end_xfer;
  input   [ 31: 0] AREA_s1_readdata;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_write;
  input            reset_n;

  wire    [  1: 0] AREA_s1_address;
  wire             AREA_s1_allgrants;
  wire             AREA_s1_allow_new_arb_cycle;
  wire             AREA_s1_any_bursting_master_saved_grant;
  wire             AREA_s1_any_continuerequest;
  wire             AREA_s1_arb_counter_enable;
  reg     [  1: 0] AREA_s1_arb_share_counter;
  wire    [  1: 0] AREA_s1_arb_share_counter_next_value;
  wire    [  1: 0] AREA_s1_arb_share_set_values;
  wire             AREA_s1_beginbursttransfer_internal;
  wire             AREA_s1_begins_xfer;
  wire             AREA_s1_end_xfer;
  wire             AREA_s1_firsttransfer;
  wire             AREA_s1_grant_vector;
  wire             AREA_s1_in_a_read_cycle;
  wire             AREA_s1_in_a_write_cycle;
  wire             AREA_s1_master_qreq_vector;
  wire             AREA_s1_non_bursting_master_requests;
  wire    [ 31: 0] AREA_s1_readdata_from_sa;
  reg              AREA_s1_reg_firsttransfer;
  wire             AREA_s1_reset_n;
  reg              AREA_s1_slavearbiterlockenable;
  wire             AREA_s1_slavearbiterlockenable2;
  wire             AREA_s1_unreg_firsttransfer;
  wire             AREA_s1_waits_for_read;
  wire             AREA_s1_waits_for_write;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_AREA_s1;
  wire             cpu_data_master_qualified_request_AREA_s1;
  wire             cpu_data_master_read_data_valid_AREA_s1;
  wire             cpu_data_master_requests_AREA_s1;
  wire             cpu_data_master_saved_grant_AREA_s1;
  reg              d1_AREA_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_AREA_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 24: 0] shifted_address_to_AREA_s1_from_cpu_data_master;
  wire             wait_for_AREA_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~AREA_s1_end_xfer;
    end


  assign AREA_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_AREA_s1));
  //assign AREA_s1_readdata_from_sa = AREA_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign AREA_s1_readdata_from_sa = AREA_s1_readdata;

  assign cpu_data_master_requests_AREA_s1 = (({cpu_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h0) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_read;
  //AREA_s1_arb_share_counter set values, which is an e_mux
  assign AREA_s1_arb_share_set_values = 1;

  //AREA_s1_non_bursting_master_requests mux, which is an e_mux
  assign AREA_s1_non_bursting_master_requests = cpu_data_master_requests_AREA_s1;

  //AREA_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign AREA_s1_any_bursting_master_saved_grant = 0;

  //AREA_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign AREA_s1_arb_share_counter_next_value = AREA_s1_firsttransfer ? (AREA_s1_arb_share_set_values - 1) : |AREA_s1_arb_share_counter ? (AREA_s1_arb_share_counter - 1) : 0;

  //AREA_s1_allgrants all slave grants, which is an e_mux
  assign AREA_s1_allgrants = |AREA_s1_grant_vector;

  //AREA_s1_end_xfer assignment, which is an e_assign
  assign AREA_s1_end_xfer = ~(AREA_s1_waits_for_read | AREA_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_AREA_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_AREA_s1 = AREA_s1_end_xfer & (~AREA_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //AREA_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign AREA_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_AREA_s1 & AREA_s1_allgrants) | (end_xfer_arb_share_counter_term_AREA_s1 & ~AREA_s1_non_bursting_master_requests);

  //AREA_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          AREA_s1_arb_share_counter <= 0;
      else if (AREA_s1_arb_counter_enable)
          AREA_s1_arb_share_counter <= AREA_s1_arb_share_counter_next_value;
    end


  //AREA_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          AREA_s1_slavearbiterlockenable <= 0;
      else if ((|AREA_s1_master_qreq_vector & end_xfer_arb_share_counter_term_AREA_s1) | (end_xfer_arb_share_counter_term_AREA_s1 & ~AREA_s1_non_bursting_master_requests))
          AREA_s1_slavearbiterlockenable <= |AREA_s1_arb_share_counter_next_value;
    end


  //cpu/data_master AREA/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = AREA_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //AREA_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign AREA_s1_slavearbiterlockenable2 = |AREA_s1_arb_share_counter_next_value;

  //cpu/data_master AREA/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = AREA_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //AREA_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign AREA_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_AREA_s1 = cpu_data_master_requests_AREA_s1;
  //master is always granted when requested
  assign cpu_data_master_granted_AREA_s1 = cpu_data_master_qualified_request_AREA_s1;

  //cpu/data_master saved-grant AREA/s1, which is an e_assign
  assign cpu_data_master_saved_grant_AREA_s1 = cpu_data_master_requests_AREA_s1;

  //allow new arb cycle for AREA/s1, which is an e_assign
  assign AREA_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign AREA_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign AREA_s1_master_qreq_vector = 1;

  //AREA_s1_reset_n assignment, which is an e_assign
  assign AREA_s1_reset_n = reset_n;

  //AREA_s1_firsttransfer first transaction, which is an e_assign
  assign AREA_s1_firsttransfer = AREA_s1_begins_xfer ? AREA_s1_unreg_firsttransfer : AREA_s1_reg_firsttransfer;

  //AREA_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign AREA_s1_unreg_firsttransfer = ~(AREA_s1_slavearbiterlockenable & AREA_s1_any_continuerequest);

  //AREA_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          AREA_s1_reg_firsttransfer <= 1'b1;
      else if (AREA_s1_begins_xfer)
          AREA_s1_reg_firsttransfer <= AREA_s1_unreg_firsttransfer;
    end


  //AREA_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign AREA_s1_beginbursttransfer_internal = AREA_s1_begins_xfer;

  assign shifted_address_to_AREA_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //AREA_s1_address mux, which is an e_mux
  assign AREA_s1_address = shifted_address_to_AREA_s1_from_cpu_data_master >> 2;

  //d1_AREA_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_AREA_s1_end_xfer <= 1;
      else if (1)
          d1_AREA_s1_end_xfer <= AREA_s1_end_xfer;
    end


  //AREA_s1_waits_for_read in a cycle, which is an e_mux
  assign AREA_s1_waits_for_read = AREA_s1_in_a_read_cycle & AREA_s1_begins_xfer;

  //AREA_s1_in_a_read_cycle assignment, which is an e_assign
  assign AREA_s1_in_a_read_cycle = cpu_data_master_granted_AREA_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = AREA_s1_in_a_read_cycle;

  //AREA_s1_waits_for_write in a cycle, which is an e_mux
  assign AREA_s1_waits_for_write = AREA_s1_in_a_write_cycle & 0;

  //AREA_s1_in_a_write_cycle assignment, which is an e_assign
  assign AREA_s1_in_a_write_cycle = cpu_data_master_granted_AREA_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = AREA_s1_in_a_write_cycle;

  assign wait_for_AREA_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //AREA/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module B1_s1_arbitrator (
                          // inputs:
                           clk,
                           cpu_data_master_address_to_slave,
                           cpu_data_master_read,
                           cpu_data_master_waitrequest,
                           cpu_data_master_write,
                           cpu_data_master_writedata,
                           reset_n,

                          // outputs:
                           B1_s1_address,
                           B1_s1_chipselect,
                           B1_s1_reset_n,
                           B1_s1_write_n,
                           B1_s1_writedata,
                           cpu_data_master_granted_B1_s1,
                           cpu_data_master_qualified_request_B1_s1,
                           cpu_data_master_read_data_valid_B1_s1,
                           cpu_data_master_requests_B1_s1,
                           d1_B1_s1_end_xfer
                        )
;

  output  [  1: 0] B1_s1_address;
  output           B1_s1_chipselect;
  output           B1_s1_reset_n;
  output           B1_s1_write_n;
  output  [ 17: 0] B1_s1_writedata;
  output           cpu_data_master_granted_B1_s1;
  output           cpu_data_master_qualified_request_B1_s1;
  output           cpu_data_master_read_data_valid_B1_s1;
  output           cpu_data_master_requests_B1_s1;
  output           d1_B1_s1_end_xfer;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] B1_s1_address;
  wire             B1_s1_allgrants;
  wire             B1_s1_allow_new_arb_cycle;
  wire             B1_s1_any_bursting_master_saved_grant;
  wire             B1_s1_any_continuerequest;
  wire             B1_s1_arb_counter_enable;
  reg     [  1: 0] B1_s1_arb_share_counter;
  wire    [  1: 0] B1_s1_arb_share_counter_next_value;
  wire    [  1: 0] B1_s1_arb_share_set_values;
  wire             B1_s1_beginbursttransfer_internal;
  wire             B1_s1_begins_xfer;
  wire             B1_s1_chipselect;
  wire             B1_s1_end_xfer;
  wire             B1_s1_firsttransfer;
  wire             B1_s1_grant_vector;
  wire             B1_s1_in_a_read_cycle;
  wire             B1_s1_in_a_write_cycle;
  wire             B1_s1_master_qreq_vector;
  wire             B1_s1_non_bursting_master_requests;
  reg              B1_s1_reg_firsttransfer;
  wire             B1_s1_reset_n;
  reg              B1_s1_slavearbiterlockenable;
  wire             B1_s1_slavearbiterlockenable2;
  wire             B1_s1_unreg_firsttransfer;
  wire             B1_s1_waits_for_read;
  wire             B1_s1_waits_for_write;
  wire             B1_s1_write_n;
  wire    [ 17: 0] B1_s1_writedata;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_B1_s1;
  wire             cpu_data_master_qualified_request_B1_s1;
  wire             cpu_data_master_read_data_valid_B1_s1;
  wire             cpu_data_master_requests_B1_s1;
  wire             cpu_data_master_saved_grant_B1_s1;
  reg              d1_B1_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_B1_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 24: 0] shifted_address_to_B1_s1_from_cpu_data_master;
  wire             wait_for_B1_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~B1_s1_end_xfer;
    end


  assign B1_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_B1_s1));
  assign cpu_data_master_requests_B1_s1 = (({cpu_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h1000) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_write;
  //B1_s1_arb_share_counter set values, which is an e_mux
  assign B1_s1_arb_share_set_values = 1;

  //B1_s1_non_bursting_master_requests mux, which is an e_mux
  assign B1_s1_non_bursting_master_requests = cpu_data_master_requests_B1_s1;

  //B1_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign B1_s1_any_bursting_master_saved_grant = 0;

  //B1_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign B1_s1_arb_share_counter_next_value = B1_s1_firsttransfer ? (B1_s1_arb_share_set_values - 1) : |B1_s1_arb_share_counter ? (B1_s1_arb_share_counter - 1) : 0;

  //B1_s1_allgrants all slave grants, which is an e_mux
  assign B1_s1_allgrants = |B1_s1_grant_vector;

  //B1_s1_end_xfer assignment, which is an e_assign
  assign B1_s1_end_xfer = ~(B1_s1_waits_for_read | B1_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_B1_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_B1_s1 = B1_s1_end_xfer & (~B1_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //B1_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign B1_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_B1_s1 & B1_s1_allgrants) | (end_xfer_arb_share_counter_term_B1_s1 & ~B1_s1_non_bursting_master_requests);

  //B1_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B1_s1_arb_share_counter <= 0;
      else if (B1_s1_arb_counter_enable)
          B1_s1_arb_share_counter <= B1_s1_arb_share_counter_next_value;
    end


  //B1_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B1_s1_slavearbiterlockenable <= 0;
      else if ((|B1_s1_master_qreq_vector & end_xfer_arb_share_counter_term_B1_s1) | (end_xfer_arb_share_counter_term_B1_s1 & ~B1_s1_non_bursting_master_requests))
          B1_s1_slavearbiterlockenable <= |B1_s1_arb_share_counter_next_value;
    end


  //cpu/data_master B1/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = B1_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //B1_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign B1_s1_slavearbiterlockenable2 = |B1_s1_arb_share_counter_next_value;

  //cpu/data_master B1/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = B1_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //B1_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign B1_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_B1_s1 = cpu_data_master_requests_B1_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //B1_s1_writedata mux, which is an e_mux
  assign B1_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_B1_s1 = cpu_data_master_qualified_request_B1_s1;

  //cpu/data_master saved-grant B1/s1, which is an e_assign
  assign cpu_data_master_saved_grant_B1_s1 = cpu_data_master_requests_B1_s1;

  //allow new arb cycle for B1/s1, which is an e_assign
  assign B1_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign B1_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign B1_s1_master_qreq_vector = 1;

  //B1_s1_reset_n assignment, which is an e_assign
  assign B1_s1_reset_n = reset_n;

  assign B1_s1_chipselect = cpu_data_master_granted_B1_s1;
  //B1_s1_firsttransfer first transaction, which is an e_assign
  assign B1_s1_firsttransfer = B1_s1_begins_xfer ? B1_s1_unreg_firsttransfer : B1_s1_reg_firsttransfer;

  //B1_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign B1_s1_unreg_firsttransfer = ~(B1_s1_slavearbiterlockenable & B1_s1_any_continuerequest);

  //B1_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B1_s1_reg_firsttransfer <= 1'b1;
      else if (B1_s1_begins_xfer)
          B1_s1_reg_firsttransfer <= B1_s1_unreg_firsttransfer;
    end


  //B1_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign B1_s1_beginbursttransfer_internal = B1_s1_begins_xfer;

  //~B1_s1_write_n assignment, which is an e_mux
  assign B1_s1_write_n = ~(cpu_data_master_granted_B1_s1 & cpu_data_master_write);

  assign shifted_address_to_B1_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //B1_s1_address mux, which is an e_mux
  assign B1_s1_address = shifted_address_to_B1_s1_from_cpu_data_master >> 2;

  //d1_B1_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_B1_s1_end_xfer <= 1;
      else if (1)
          d1_B1_s1_end_xfer <= B1_s1_end_xfer;
    end


  //B1_s1_waits_for_read in a cycle, which is an e_mux
  assign B1_s1_waits_for_read = B1_s1_in_a_read_cycle & B1_s1_begins_xfer;

  //B1_s1_in_a_read_cycle assignment, which is an e_assign
  assign B1_s1_in_a_read_cycle = cpu_data_master_granted_B1_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = B1_s1_in_a_read_cycle;

  //B1_s1_waits_for_write in a cycle, which is an e_mux
  assign B1_s1_waits_for_write = B1_s1_in_a_write_cycle & 0;

  //B1_s1_in_a_write_cycle assignment, which is an e_assign
  assign B1_s1_in_a_write_cycle = cpu_data_master_granted_B1_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = B1_s1_in_a_write_cycle;

  assign wait_for_B1_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //B1/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module B2_s1_arbitrator (
                          // inputs:
                           clk,
                           cpu_data_master_address_to_slave,
                           cpu_data_master_read,
                           cpu_data_master_waitrequest,
                           cpu_data_master_write,
                           cpu_data_master_writedata,
                           reset_n,

                          // outputs:
                           B2_s1_address,
                           B2_s1_chipselect,
                           B2_s1_reset_n,
                           B2_s1_write_n,
                           B2_s1_writedata,
                           cpu_data_master_granted_B2_s1,
                           cpu_data_master_qualified_request_B2_s1,
                           cpu_data_master_read_data_valid_B2_s1,
                           cpu_data_master_requests_B2_s1,
                           d1_B2_s1_end_xfer
                        )
;

  output  [  1: 0] B2_s1_address;
  output           B2_s1_chipselect;
  output           B2_s1_reset_n;
  output           B2_s1_write_n;
  output  [ 17: 0] B2_s1_writedata;
  output           cpu_data_master_granted_B2_s1;
  output           cpu_data_master_qualified_request_B2_s1;
  output           cpu_data_master_read_data_valid_B2_s1;
  output           cpu_data_master_requests_B2_s1;
  output           d1_B2_s1_end_xfer;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] B2_s1_address;
  wire             B2_s1_allgrants;
  wire             B2_s1_allow_new_arb_cycle;
  wire             B2_s1_any_bursting_master_saved_grant;
  wire             B2_s1_any_continuerequest;
  wire             B2_s1_arb_counter_enable;
  reg     [  1: 0] B2_s1_arb_share_counter;
  wire    [  1: 0] B2_s1_arb_share_counter_next_value;
  wire    [  1: 0] B2_s1_arb_share_set_values;
  wire             B2_s1_beginbursttransfer_internal;
  wire             B2_s1_begins_xfer;
  wire             B2_s1_chipselect;
  wire             B2_s1_end_xfer;
  wire             B2_s1_firsttransfer;
  wire             B2_s1_grant_vector;
  wire             B2_s1_in_a_read_cycle;
  wire             B2_s1_in_a_write_cycle;
  wire             B2_s1_master_qreq_vector;
  wire             B2_s1_non_bursting_master_requests;
  reg              B2_s1_reg_firsttransfer;
  wire             B2_s1_reset_n;
  reg              B2_s1_slavearbiterlockenable;
  wire             B2_s1_slavearbiterlockenable2;
  wire             B2_s1_unreg_firsttransfer;
  wire             B2_s1_waits_for_read;
  wire             B2_s1_waits_for_write;
  wire             B2_s1_write_n;
  wire    [ 17: 0] B2_s1_writedata;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_B2_s1;
  wire             cpu_data_master_qualified_request_B2_s1;
  wire             cpu_data_master_read_data_valid_B2_s1;
  wire             cpu_data_master_requests_B2_s1;
  wire             cpu_data_master_saved_grant_B2_s1;
  reg              d1_B2_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_B2_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 24: 0] shifted_address_to_B2_s1_from_cpu_data_master;
  wire             wait_for_B2_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~B2_s1_end_xfer;
    end


  assign B2_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_B2_s1));
  assign cpu_data_master_requests_B2_s1 = (({cpu_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h1010) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_write;
  //B2_s1_arb_share_counter set values, which is an e_mux
  assign B2_s1_arb_share_set_values = 1;

  //B2_s1_non_bursting_master_requests mux, which is an e_mux
  assign B2_s1_non_bursting_master_requests = cpu_data_master_requests_B2_s1;

  //B2_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign B2_s1_any_bursting_master_saved_grant = 0;

  //B2_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign B2_s1_arb_share_counter_next_value = B2_s1_firsttransfer ? (B2_s1_arb_share_set_values - 1) : |B2_s1_arb_share_counter ? (B2_s1_arb_share_counter - 1) : 0;

  //B2_s1_allgrants all slave grants, which is an e_mux
  assign B2_s1_allgrants = |B2_s1_grant_vector;

  //B2_s1_end_xfer assignment, which is an e_assign
  assign B2_s1_end_xfer = ~(B2_s1_waits_for_read | B2_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_B2_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_B2_s1 = B2_s1_end_xfer & (~B2_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //B2_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign B2_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_B2_s1 & B2_s1_allgrants) | (end_xfer_arb_share_counter_term_B2_s1 & ~B2_s1_non_bursting_master_requests);

  //B2_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B2_s1_arb_share_counter <= 0;
      else if (B2_s1_arb_counter_enable)
          B2_s1_arb_share_counter <= B2_s1_arb_share_counter_next_value;
    end


  //B2_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B2_s1_slavearbiterlockenable <= 0;
      else if ((|B2_s1_master_qreq_vector & end_xfer_arb_share_counter_term_B2_s1) | (end_xfer_arb_share_counter_term_B2_s1 & ~B2_s1_non_bursting_master_requests))
          B2_s1_slavearbiterlockenable <= |B2_s1_arb_share_counter_next_value;
    end


  //cpu/data_master B2/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = B2_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //B2_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign B2_s1_slavearbiterlockenable2 = |B2_s1_arb_share_counter_next_value;

  //cpu/data_master B2/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = B2_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //B2_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign B2_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_B2_s1 = cpu_data_master_requests_B2_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //B2_s1_writedata mux, which is an e_mux
  assign B2_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_B2_s1 = cpu_data_master_qualified_request_B2_s1;

  //cpu/data_master saved-grant B2/s1, which is an e_assign
  assign cpu_data_master_saved_grant_B2_s1 = cpu_data_master_requests_B2_s1;

  //allow new arb cycle for B2/s1, which is an e_assign
  assign B2_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign B2_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign B2_s1_master_qreq_vector = 1;

  //B2_s1_reset_n assignment, which is an e_assign
  assign B2_s1_reset_n = reset_n;

  assign B2_s1_chipselect = cpu_data_master_granted_B2_s1;
  //B2_s1_firsttransfer first transaction, which is an e_assign
  assign B2_s1_firsttransfer = B2_s1_begins_xfer ? B2_s1_unreg_firsttransfer : B2_s1_reg_firsttransfer;

  //B2_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign B2_s1_unreg_firsttransfer = ~(B2_s1_slavearbiterlockenable & B2_s1_any_continuerequest);

  //B2_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B2_s1_reg_firsttransfer <= 1'b1;
      else if (B2_s1_begins_xfer)
          B2_s1_reg_firsttransfer <= B2_s1_unreg_firsttransfer;
    end


  //B2_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign B2_s1_beginbursttransfer_internal = B2_s1_begins_xfer;

  //~B2_s1_write_n assignment, which is an e_mux
  assign B2_s1_write_n = ~(cpu_data_master_granted_B2_s1 & cpu_data_master_write);

  assign shifted_address_to_B2_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //B2_s1_address mux, which is an e_mux
  assign B2_s1_address = shifted_address_to_B2_s1_from_cpu_data_master >> 2;

  //d1_B2_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_B2_s1_end_xfer <= 1;
      else if (1)
          d1_B2_s1_end_xfer <= B2_s1_end_xfer;
    end


  //B2_s1_waits_for_read in a cycle, which is an e_mux
  assign B2_s1_waits_for_read = B2_s1_in_a_read_cycle & B2_s1_begins_xfer;

  //B2_s1_in_a_read_cycle assignment, which is an e_assign
  assign B2_s1_in_a_read_cycle = cpu_data_master_granted_B2_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = B2_s1_in_a_read_cycle;

  //B2_s1_waits_for_write in a cycle, which is an e_mux
  assign B2_s1_waits_for_write = B2_s1_in_a_write_cycle & 0;

  //B2_s1_in_a_write_cycle assignment, which is an e_assign
  assign B2_s1_in_a_write_cycle = cpu_data_master_granted_B2_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = B2_s1_in_a_write_cycle;

  assign wait_for_B2_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //B2/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module B3_s1_arbitrator (
                          // inputs:
                           clk,
                           cpu_data_master_address_to_slave,
                           cpu_data_master_read,
                           cpu_data_master_waitrequest,
                           cpu_data_master_write,
                           cpu_data_master_writedata,
                           reset_n,

                          // outputs:
                           B3_s1_address,
                           B3_s1_chipselect,
                           B3_s1_reset_n,
                           B3_s1_write_n,
                           B3_s1_writedata,
                           cpu_data_master_granted_B3_s1,
                           cpu_data_master_qualified_request_B3_s1,
                           cpu_data_master_read_data_valid_B3_s1,
                           cpu_data_master_requests_B3_s1,
                           d1_B3_s1_end_xfer
                        )
;

  output  [  1: 0] B3_s1_address;
  output           B3_s1_chipselect;
  output           B3_s1_reset_n;
  output           B3_s1_write_n;
  output  [ 17: 0] B3_s1_writedata;
  output           cpu_data_master_granted_B3_s1;
  output           cpu_data_master_qualified_request_B3_s1;
  output           cpu_data_master_read_data_valid_B3_s1;
  output           cpu_data_master_requests_B3_s1;
  output           d1_B3_s1_end_xfer;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] B3_s1_address;
  wire             B3_s1_allgrants;
  wire             B3_s1_allow_new_arb_cycle;
  wire             B3_s1_any_bursting_master_saved_grant;
  wire             B3_s1_any_continuerequest;
  wire             B3_s1_arb_counter_enable;
  reg     [  1: 0] B3_s1_arb_share_counter;
  wire    [  1: 0] B3_s1_arb_share_counter_next_value;
  wire    [  1: 0] B3_s1_arb_share_set_values;
  wire             B3_s1_beginbursttransfer_internal;
  wire             B3_s1_begins_xfer;
  wire             B3_s1_chipselect;
  wire             B3_s1_end_xfer;
  wire             B3_s1_firsttransfer;
  wire             B3_s1_grant_vector;
  wire             B3_s1_in_a_read_cycle;
  wire             B3_s1_in_a_write_cycle;
  wire             B3_s1_master_qreq_vector;
  wire             B3_s1_non_bursting_master_requests;
  reg              B3_s1_reg_firsttransfer;
  wire             B3_s1_reset_n;
  reg              B3_s1_slavearbiterlockenable;
  wire             B3_s1_slavearbiterlockenable2;
  wire             B3_s1_unreg_firsttransfer;
  wire             B3_s1_waits_for_read;
  wire             B3_s1_waits_for_write;
  wire             B3_s1_write_n;
  wire    [ 17: 0] B3_s1_writedata;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_B3_s1;
  wire             cpu_data_master_qualified_request_B3_s1;
  wire             cpu_data_master_read_data_valid_B3_s1;
  wire             cpu_data_master_requests_B3_s1;
  wire             cpu_data_master_saved_grant_B3_s1;
  reg              d1_B3_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_B3_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 24: 0] shifted_address_to_B3_s1_from_cpu_data_master;
  wire             wait_for_B3_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~B3_s1_end_xfer;
    end


  assign B3_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_B3_s1));
  assign cpu_data_master_requests_B3_s1 = (({cpu_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h1020) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_write;
  //B3_s1_arb_share_counter set values, which is an e_mux
  assign B3_s1_arb_share_set_values = 1;

  //B3_s1_non_bursting_master_requests mux, which is an e_mux
  assign B3_s1_non_bursting_master_requests = cpu_data_master_requests_B3_s1;

  //B3_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign B3_s1_any_bursting_master_saved_grant = 0;

  //B3_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign B3_s1_arb_share_counter_next_value = B3_s1_firsttransfer ? (B3_s1_arb_share_set_values - 1) : |B3_s1_arb_share_counter ? (B3_s1_arb_share_counter - 1) : 0;

  //B3_s1_allgrants all slave grants, which is an e_mux
  assign B3_s1_allgrants = |B3_s1_grant_vector;

  //B3_s1_end_xfer assignment, which is an e_assign
  assign B3_s1_end_xfer = ~(B3_s1_waits_for_read | B3_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_B3_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_B3_s1 = B3_s1_end_xfer & (~B3_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //B3_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign B3_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_B3_s1 & B3_s1_allgrants) | (end_xfer_arb_share_counter_term_B3_s1 & ~B3_s1_non_bursting_master_requests);

  //B3_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B3_s1_arb_share_counter <= 0;
      else if (B3_s1_arb_counter_enable)
          B3_s1_arb_share_counter <= B3_s1_arb_share_counter_next_value;
    end


  //B3_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B3_s1_slavearbiterlockenable <= 0;
      else if ((|B3_s1_master_qreq_vector & end_xfer_arb_share_counter_term_B3_s1) | (end_xfer_arb_share_counter_term_B3_s1 & ~B3_s1_non_bursting_master_requests))
          B3_s1_slavearbiterlockenable <= |B3_s1_arb_share_counter_next_value;
    end


  //cpu/data_master B3/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = B3_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //B3_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign B3_s1_slavearbiterlockenable2 = |B3_s1_arb_share_counter_next_value;

  //cpu/data_master B3/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = B3_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //B3_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign B3_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_B3_s1 = cpu_data_master_requests_B3_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //B3_s1_writedata mux, which is an e_mux
  assign B3_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_B3_s1 = cpu_data_master_qualified_request_B3_s1;

  //cpu/data_master saved-grant B3/s1, which is an e_assign
  assign cpu_data_master_saved_grant_B3_s1 = cpu_data_master_requests_B3_s1;

  //allow new arb cycle for B3/s1, which is an e_assign
  assign B3_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign B3_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign B3_s1_master_qreq_vector = 1;

  //B3_s1_reset_n assignment, which is an e_assign
  assign B3_s1_reset_n = reset_n;

  assign B3_s1_chipselect = cpu_data_master_granted_B3_s1;
  //B3_s1_firsttransfer first transaction, which is an e_assign
  assign B3_s1_firsttransfer = B3_s1_begins_xfer ? B3_s1_unreg_firsttransfer : B3_s1_reg_firsttransfer;

  //B3_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign B3_s1_unreg_firsttransfer = ~(B3_s1_slavearbiterlockenable & B3_s1_any_continuerequest);

  //B3_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B3_s1_reg_firsttransfer <= 1'b1;
      else if (B3_s1_begins_xfer)
          B3_s1_reg_firsttransfer <= B3_s1_unreg_firsttransfer;
    end


  //B3_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign B3_s1_beginbursttransfer_internal = B3_s1_begins_xfer;

  //~B3_s1_write_n assignment, which is an e_mux
  assign B3_s1_write_n = ~(cpu_data_master_granted_B3_s1 & cpu_data_master_write);

  assign shifted_address_to_B3_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //B3_s1_address mux, which is an e_mux
  assign B3_s1_address = shifted_address_to_B3_s1_from_cpu_data_master >> 2;

  //d1_B3_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_B3_s1_end_xfer <= 1;
      else if (1)
          d1_B3_s1_end_xfer <= B3_s1_end_xfer;
    end


  //B3_s1_waits_for_read in a cycle, which is an e_mux
  assign B3_s1_waits_for_read = B3_s1_in_a_read_cycle & B3_s1_begins_xfer;

  //B3_s1_in_a_read_cycle assignment, which is an e_assign
  assign B3_s1_in_a_read_cycle = cpu_data_master_granted_B3_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = B3_s1_in_a_read_cycle;

  //B3_s1_waits_for_write in a cycle, which is an e_mux
  assign B3_s1_waits_for_write = B3_s1_in_a_write_cycle & 0;

  //B3_s1_in_a_write_cycle assignment, which is an e_assign
  assign B3_s1_in_a_write_cycle = cpu_data_master_granted_B3_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = B3_s1_in_a_write_cycle;

  assign wait_for_B3_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //B3/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module B4_s1_arbitrator (
                          // inputs:
                           clk,
                           cpu_data_master_address_to_slave,
                           cpu_data_master_read,
                           cpu_data_master_waitrequest,
                           cpu_data_master_write,
                           cpu_data_master_writedata,
                           reset_n,

                          // outputs:
                           B4_s1_address,
                           B4_s1_chipselect,
                           B4_s1_reset_n,
                           B4_s1_write_n,
                           B4_s1_writedata,
                           cpu_data_master_granted_B4_s1,
                           cpu_data_master_qualified_request_B4_s1,
                           cpu_data_master_read_data_valid_B4_s1,
                           cpu_data_master_requests_B4_s1,
                           d1_B4_s1_end_xfer
                        )
;

  output  [  1: 0] B4_s1_address;
  output           B4_s1_chipselect;
  output           B4_s1_reset_n;
  output           B4_s1_write_n;
  output  [ 17: 0] B4_s1_writedata;
  output           cpu_data_master_granted_B4_s1;
  output           cpu_data_master_qualified_request_B4_s1;
  output           cpu_data_master_read_data_valid_B4_s1;
  output           cpu_data_master_requests_B4_s1;
  output           d1_B4_s1_end_xfer;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] B4_s1_address;
  wire             B4_s1_allgrants;
  wire             B4_s1_allow_new_arb_cycle;
  wire             B4_s1_any_bursting_master_saved_grant;
  wire             B4_s1_any_continuerequest;
  wire             B4_s1_arb_counter_enable;
  reg     [  1: 0] B4_s1_arb_share_counter;
  wire    [  1: 0] B4_s1_arb_share_counter_next_value;
  wire    [  1: 0] B4_s1_arb_share_set_values;
  wire             B4_s1_beginbursttransfer_internal;
  wire             B4_s1_begins_xfer;
  wire             B4_s1_chipselect;
  wire             B4_s1_end_xfer;
  wire             B4_s1_firsttransfer;
  wire             B4_s1_grant_vector;
  wire             B4_s1_in_a_read_cycle;
  wire             B4_s1_in_a_write_cycle;
  wire             B4_s1_master_qreq_vector;
  wire             B4_s1_non_bursting_master_requests;
  reg              B4_s1_reg_firsttransfer;
  wire             B4_s1_reset_n;
  reg              B4_s1_slavearbiterlockenable;
  wire             B4_s1_slavearbiterlockenable2;
  wire             B4_s1_unreg_firsttransfer;
  wire             B4_s1_waits_for_read;
  wire             B4_s1_waits_for_write;
  wire             B4_s1_write_n;
  wire    [ 17: 0] B4_s1_writedata;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_B4_s1;
  wire             cpu_data_master_qualified_request_B4_s1;
  wire             cpu_data_master_read_data_valid_B4_s1;
  wire             cpu_data_master_requests_B4_s1;
  wire             cpu_data_master_saved_grant_B4_s1;
  reg              d1_B4_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_B4_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 24: 0] shifted_address_to_B4_s1_from_cpu_data_master;
  wire             wait_for_B4_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~B4_s1_end_xfer;
    end


  assign B4_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_B4_s1));
  assign cpu_data_master_requests_B4_s1 = (({cpu_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h1030) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_write;
  //B4_s1_arb_share_counter set values, which is an e_mux
  assign B4_s1_arb_share_set_values = 1;

  //B4_s1_non_bursting_master_requests mux, which is an e_mux
  assign B4_s1_non_bursting_master_requests = cpu_data_master_requests_B4_s1;

  //B4_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign B4_s1_any_bursting_master_saved_grant = 0;

  //B4_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign B4_s1_arb_share_counter_next_value = B4_s1_firsttransfer ? (B4_s1_arb_share_set_values - 1) : |B4_s1_arb_share_counter ? (B4_s1_arb_share_counter - 1) : 0;

  //B4_s1_allgrants all slave grants, which is an e_mux
  assign B4_s1_allgrants = |B4_s1_grant_vector;

  //B4_s1_end_xfer assignment, which is an e_assign
  assign B4_s1_end_xfer = ~(B4_s1_waits_for_read | B4_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_B4_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_B4_s1 = B4_s1_end_xfer & (~B4_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //B4_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign B4_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_B4_s1 & B4_s1_allgrants) | (end_xfer_arb_share_counter_term_B4_s1 & ~B4_s1_non_bursting_master_requests);

  //B4_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B4_s1_arb_share_counter <= 0;
      else if (B4_s1_arb_counter_enable)
          B4_s1_arb_share_counter <= B4_s1_arb_share_counter_next_value;
    end


  //B4_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B4_s1_slavearbiterlockenable <= 0;
      else if ((|B4_s1_master_qreq_vector & end_xfer_arb_share_counter_term_B4_s1) | (end_xfer_arb_share_counter_term_B4_s1 & ~B4_s1_non_bursting_master_requests))
          B4_s1_slavearbiterlockenable <= |B4_s1_arb_share_counter_next_value;
    end


  //cpu/data_master B4/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = B4_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //B4_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign B4_s1_slavearbiterlockenable2 = |B4_s1_arb_share_counter_next_value;

  //cpu/data_master B4/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = B4_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //B4_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign B4_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_B4_s1 = cpu_data_master_requests_B4_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //B4_s1_writedata mux, which is an e_mux
  assign B4_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_B4_s1 = cpu_data_master_qualified_request_B4_s1;

  //cpu/data_master saved-grant B4/s1, which is an e_assign
  assign cpu_data_master_saved_grant_B4_s1 = cpu_data_master_requests_B4_s1;

  //allow new arb cycle for B4/s1, which is an e_assign
  assign B4_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign B4_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign B4_s1_master_qreq_vector = 1;

  //B4_s1_reset_n assignment, which is an e_assign
  assign B4_s1_reset_n = reset_n;

  assign B4_s1_chipselect = cpu_data_master_granted_B4_s1;
  //B4_s1_firsttransfer first transaction, which is an e_assign
  assign B4_s1_firsttransfer = B4_s1_begins_xfer ? B4_s1_unreg_firsttransfer : B4_s1_reg_firsttransfer;

  //B4_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign B4_s1_unreg_firsttransfer = ~(B4_s1_slavearbiterlockenable & B4_s1_any_continuerequest);

  //B4_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B4_s1_reg_firsttransfer <= 1'b1;
      else if (B4_s1_begins_xfer)
          B4_s1_reg_firsttransfer <= B4_s1_unreg_firsttransfer;
    end


  //B4_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign B4_s1_beginbursttransfer_internal = B4_s1_begins_xfer;

  //~B4_s1_write_n assignment, which is an e_mux
  assign B4_s1_write_n = ~(cpu_data_master_granted_B4_s1 & cpu_data_master_write);

  assign shifted_address_to_B4_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //B4_s1_address mux, which is an e_mux
  assign B4_s1_address = shifted_address_to_B4_s1_from_cpu_data_master >> 2;

  //d1_B4_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_B4_s1_end_xfer <= 1;
      else if (1)
          d1_B4_s1_end_xfer <= B4_s1_end_xfer;
    end


  //B4_s1_waits_for_read in a cycle, which is an e_mux
  assign B4_s1_waits_for_read = B4_s1_in_a_read_cycle & B4_s1_begins_xfer;

  //B4_s1_in_a_read_cycle assignment, which is an e_assign
  assign B4_s1_in_a_read_cycle = cpu_data_master_granted_B4_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = B4_s1_in_a_read_cycle;

  //B4_s1_waits_for_write in a cycle, which is an e_mux
  assign B4_s1_waits_for_write = B4_s1_in_a_write_cycle & 0;

  //B4_s1_in_a_write_cycle assignment, which is an e_assign
  assign B4_s1_in_a_write_cycle = cpu_data_master_granted_B4_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = B4_s1_in_a_write_cycle;

  assign wait_for_B4_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //B4/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module B5_s1_arbitrator (
                          // inputs:
                           clk,
                           cpu_data_master_address_to_slave,
                           cpu_data_master_read,
                           cpu_data_master_waitrequest,
                           cpu_data_master_write,
                           cpu_data_master_writedata,
                           reset_n,

                          // outputs:
                           B5_s1_address,
                           B5_s1_chipselect,
                           B5_s1_reset_n,
                           B5_s1_write_n,
                           B5_s1_writedata,
                           cpu_data_master_granted_B5_s1,
                           cpu_data_master_qualified_request_B5_s1,
                           cpu_data_master_read_data_valid_B5_s1,
                           cpu_data_master_requests_B5_s1,
                           d1_B5_s1_end_xfer
                        )
;

  output  [  1: 0] B5_s1_address;
  output           B5_s1_chipselect;
  output           B5_s1_reset_n;
  output           B5_s1_write_n;
  output  [ 17: 0] B5_s1_writedata;
  output           cpu_data_master_granted_B5_s1;
  output           cpu_data_master_qualified_request_B5_s1;
  output           cpu_data_master_read_data_valid_B5_s1;
  output           cpu_data_master_requests_B5_s1;
  output           d1_B5_s1_end_xfer;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] B5_s1_address;
  wire             B5_s1_allgrants;
  wire             B5_s1_allow_new_arb_cycle;
  wire             B5_s1_any_bursting_master_saved_grant;
  wire             B5_s1_any_continuerequest;
  wire             B5_s1_arb_counter_enable;
  reg     [  1: 0] B5_s1_arb_share_counter;
  wire    [  1: 0] B5_s1_arb_share_counter_next_value;
  wire    [  1: 0] B5_s1_arb_share_set_values;
  wire             B5_s1_beginbursttransfer_internal;
  wire             B5_s1_begins_xfer;
  wire             B5_s1_chipselect;
  wire             B5_s1_end_xfer;
  wire             B5_s1_firsttransfer;
  wire             B5_s1_grant_vector;
  wire             B5_s1_in_a_read_cycle;
  wire             B5_s1_in_a_write_cycle;
  wire             B5_s1_master_qreq_vector;
  wire             B5_s1_non_bursting_master_requests;
  reg              B5_s1_reg_firsttransfer;
  wire             B5_s1_reset_n;
  reg              B5_s1_slavearbiterlockenable;
  wire             B5_s1_slavearbiterlockenable2;
  wire             B5_s1_unreg_firsttransfer;
  wire             B5_s1_waits_for_read;
  wire             B5_s1_waits_for_write;
  wire             B5_s1_write_n;
  wire    [ 17: 0] B5_s1_writedata;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_B5_s1;
  wire             cpu_data_master_qualified_request_B5_s1;
  wire             cpu_data_master_read_data_valid_B5_s1;
  wire             cpu_data_master_requests_B5_s1;
  wire             cpu_data_master_saved_grant_B5_s1;
  reg              d1_B5_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_B5_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 24: 0] shifted_address_to_B5_s1_from_cpu_data_master;
  wire             wait_for_B5_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~B5_s1_end_xfer;
    end


  assign B5_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_B5_s1));
  assign cpu_data_master_requests_B5_s1 = (({cpu_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h1040) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_write;
  //B5_s1_arb_share_counter set values, which is an e_mux
  assign B5_s1_arb_share_set_values = 1;

  //B5_s1_non_bursting_master_requests mux, which is an e_mux
  assign B5_s1_non_bursting_master_requests = cpu_data_master_requests_B5_s1;

  //B5_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign B5_s1_any_bursting_master_saved_grant = 0;

  //B5_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign B5_s1_arb_share_counter_next_value = B5_s1_firsttransfer ? (B5_s1_arb_share_set_values - 1) : |B5_s1_arb_share_counter ? (B5_s1_arb_share_counter - 1) : 0;

  //B5_s1_allgrants all slave grants, which is an e_mux
  assign B5_s1_allgrants = |B5_s1_grant_vector;

  //B5_s1_end_xfer assignment, which is an e_assign
  assign B5_s1_end_xfer = ~(B5_s1_waits_for_read | B5_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_B5_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_B5_s1 = B5_s1_end_xfer & (~B5_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //B5_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign B5_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_B5_s1 & B5_s1_allgrants) | (end_xfer_arb_share_counter_term_B5_s1 & ~B5_s1_non_bursting_master_requests);

  //B5_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B5_s1_arb_share_counter <= 0;
      else if (B5_s1_arb_counter_enable)
          B5_s1_arb_share_counter <= B5_s1_arb_share_counter_next_value;
    end


  //B5_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B5_s1_slavearbiterlockenable <= 0;
      else if ((|B5_s1_master_qreq_vector & end_xfer_arb_share_counter_term_B5_s1) | (end_xfer_arb_share_counter_term_B5_s1 & ~B5_s1_non_bursting_master_requests))
          B5_s1_slavearbiterlockenable <= |B5_s1_arb_share_counter_next_value;
    end


  //cpu/data_master B5/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = B5_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //B5_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign B5_s1_slavearbiterlockenable2 = |B5_s1_arb_share_counter_next_value;

  //cpu/data_master B5/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = B5_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //B5_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign B5_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_B5_s1 = cpu_data_master_requests_B5_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //B5_s1_writedata mux, which is an e_mux
  assign B5_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_B5_s1 = cpu_data_master_qualified_request_B5_s1;

  //cpu/data_master saved-grant B5/s1, which is an e_assign
  assign cpu_data_master_saved_grant_B5_s1 = cpu_data_master_requests_B5_s1;

  //allow new arb cycle for B5/s1, which is an e_assign
  assign B5_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign B5_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign B5_s1_master_qreq_vector = 1;

  //B5_s1_reset_n assignment, which is an e_assign
  assign B5_s1_reset_n = reset_n;

  assign B5_s1_chipselect = cpu_data_master_granted_B5_s1;
  //B5_s1_firsttransfer first transaction, which is an e_assign
  assign B5_s1_firsttransfer = B5_s1_begins_xfer ? B5_s1_unreg_firsttransfer : B5_s1_reg_firsttransfer;

  //B5_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign B5_s1_unreg_firsttransfer = ~(B5_s1_slavearbiterlockenable & B5_s1_any_continuerequest);

  //B5_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B5_s1_reg_firsttransfer <= 1'b1;
      else if (B5_s1_begins_xfer)
          B5_s1_reg_firsttransfer <= B5_s1_unreg_firsttransfer;
    end


  //B5_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign B5_s1_beginbursttransfer_internal = B5_s1_begins_xfer;

  //~B5_s1_write_n assignment, which is an e_mux
  assign B5_s1_write_n = ~(cpu_data_master_granted_B5_s1 & cpu_data_master_write);

  assign shifted_address_to_B5_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //B5_s1_address mux, which is an e_mux
  assign B5_s1_address = shifted_address_to_B5_s1_from_cpu_data_master >> 2;

  //d1_B5_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_B5_s1_end_xfer <= 1;
      else if (1)
          d1_B5_s1_end_xfer <= B5_s1_end_xfer;
    end


  //B5_s1_waits_for_read in a cycle, which is an e_mux
  assign B5_s1_waits_for_read = B5_s1_in_a_read_cycle & B5_s1_begins_xfer;

  //B5_s1_in_a_read_cycle assignment, which is an e_assign
  assign B5_s1_in_a_read_cycle = cpu_data_master_granted_B5_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = B5_s1_in_a_read_cycle;

  //B5_s1_waits_for_write in a cycle, which is an e_mux
  assign B5_s1_waits_for_write = B5_s1_in_a_write_cycle & 0;

  //B5_s1_in_a_write_cycle assignment, which is an e_assign
  assign B5_s1_in_a_write_cycle = cpu_data_master_granted_B5_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = B5_s1_in_a_write_cycle;

  assign wait_for_B5_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //B5/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module B6_s1_arbitrator (
                          // inputs:
                           clk,
                           cpu_data_master_address_to_slave,
                           cpu_data_master_read,
                           cpu_data_master_waitrequest,
                           cpu_data_master_write,
                           cpu_data_master_writedata,
                           reset_n,

                          // outputs:
                           B6_s1_address,
                           B6_s1_chipselect,
                           B6_s1_reset_n,
                           B6_s1_write_n,
                           B6_s1_writedata,
                           cpu_data_master_granted_B6_s1,
                           cpu_data_master_qualified_request_B6_s1,
                           cpu_data_master_read_data_valid_B6_s1,
                           cpu_data_master_requests_B6_s1,
                           d1_B6_s1_end_xfer
                        )
;

  output  [  1: 0] B6_s1_address;
  output           B6_s1_chipselect;
  output           B6_s1_reset_n;
  output           B6_s1_write_n;
  output  [ 17: 0] B6_s1_writedata;
  output           cpu_data_master_granted_B6_s1;
  output           cpu_data_master_qualified_request_B6_s1;
  output           cpu_data_master_read_data_valid_B6_s1;
  output           cpu_data_master_requests_B6_s1;
  output           d1_B6_s1_end_xfer;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] B6_s1_address;
  wire             B6_s1_allgrants;
  wire             B6_s1_allow_new_arb_cycle;
  wire             B6_s1_any_bursting_master_saved_grant;
  wire             B6_s1_any_continuerequest;
  wire             B6_s1_arb_counter_enable;
  reg     [  1: 0] B6_s1_arb_share_counter;
  wire    [  1: 0] B6_s1_arb_share_counter_next_value;
  wire    [  1: 0] B6_s1_arb_share_set_values;
  wire             B6_s1_beginbursttransfer_internal;
  wire             B6_s1_begins_xfer;
  wire             B6_s1_chipselect;
  wire             B6_s1_end_xfer;
  wire             B6_s1_firsttransfer;
  wire             B6_s1_grant_vector;
  wire             B6_s1_in_a_read_cycle;
  wire             B6_s1_in_a_write_cycle;
  wire             B6_s1_master_qreq_vector;
  wire             B6_s1_non_bursting_master_requests;
  reg              B6_s1_reg_firsttransfer;
  wire             B6_s1_reset_n;
  reg              B6_s1_slavearbiterlockenable;
  wire             B6_s1_slavearbiterlockenable2;
  wire             B6_s1_unreg_firsttransfer;
  wire             B6_s1_waits_for_read;
  wire             B6_s1_waits_for_write;
  wire             B6_s1_write_n;
  wire    [ 17: 0] B6_s1_writedata;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_B6_s1;
  wire             cpu_data_master_qualified_request_B6_s1;
  wire             cpu_data_master_read_data_valid_B6_s1;
  wire             cpu_data_master_requests_B6_s1;
  wire             cpu_data_master_saved_grant_B6_s1;
  reg              d1_B6_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_B6_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 24: 0] shifted_address_to_B6_s1_from_cpu_data_master;
  wire             wait_for_B6_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~B6_s1_end_xfer;
    end


  assign B6_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_B6_s1));
  assign cpu_data_master_requests_B6_s1 = (({cpu_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h1050) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_write;
  //B6_s1_arb_share_counter set values, which is an e_mux
  assign B6_s1_arb_share_set_values = 1;

  //B6_s1_non_bursting_master_requests mux, which is an e_mux
  assign B6_s1_non_bursting_master_requests = cpu_data_master_requests_B6_s1;

  //B6_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign B6_s1_any_bursting_master_saved_grant = 0;

  //B6_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign B6_s1_arb_share_counter_next_value = B6_s1_firsttransfer ? (B6_s1_arb_share_set_values - 1) : |B6_s1_arb_share_counter ? (B6_s1_arb_share_counter - 1) : 0;

  //B6_s1_allgrants all slave grants, which is an e_mux
  assign B6_s1_allgrants = |B6_s1_grant_vector;

  //B6_s1_end_xfer assignment, which is an e_assign
  assign B6_s1_end_xfer = ~(B6_s1_waits_for_read | B6_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_B6_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_B6_s1 = B6_s1_end_xfer & (~B6_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //B6_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign B6_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_B6_s1 & B6_s1_allgrants) | (end_xfer_arb_share_counter_term_B6_s1 & ~B6_s1_non_bursting_master_requests);

  //B6_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B6_s1_arb_share_counter <= 0;
      else if (B6_s1_arb_counter_enable)
          B6_s1_arb_share_counter <= B6_s1_arb_share_counter_next_value;
    end


  //B6_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B6_s1_slavearbiterlockenable <= 0;
      else if ((|B6_s1_master_qreq_vector & end_xfer_arb_share_counter_term_B6_s1) | (end_xfer_arb_share_counter_term_B6_s1 & ~B6_s1_non_bursting_master_requests))
          B6_s1_slavearbiterlockenable <= |B6_s1_arb_share_counter_next_value;
    end


  //cpu/data_master B6/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = B6_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //B6_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign B6_s1_slavearbiterlockenable2 = |B6_s1_arb_share_counter_next_value;

  //cpu/data_master B6/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = B6_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //B6_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign B6_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_B6_s1 = cpu_data_master_requests_B6_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //B6_s1_writedata mux, which is an e_mux
  assign B6_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_B6_s1 = cpu_data_master_qualified_request_B6_s1;

  //cpu/data_master saved-grant B6/s1, which is an e_assign
  assign cpu_data_master_saved_grant_B6_s1 = cpu_data_master_requests_B6_s1;

  //allow new arb cycle for B6/s1, which is an e_assign
  assign B6_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign B6_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign B6_s1_master_qreq_vector = 1;

  //B6_s1_reset_n assignment, which is an e_assign
  assign B6_s1_reset_n = reset_n;

  assign B6_s1_chipselect = cpu_data_master_granted_B6_s1;
  //B6_s1_firsttransfer first transaction, which is an e_assign
  assign B6_s1_firsttransfer = B6_s1_begins_xfer ? B6_s1_unreg_firsttransfer : B6_s1_reg_firsttransfer;

  //B6_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign B6_s1_unreg_firsttransfer = ~(B6_s1_slavearbiterlockenable & B6_s1_any_continuerequest);

  //B6_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B6_s1_reg_firsttransfer <= 1'b1;
      else if (B6_s1_begins_xfer)
          B6_s1_reg_firsttransfer <= B6_s1_unreg_firsttransfer;
    end


  //B6_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign B6_s1_beginbursttransfer_internal = B6_s1_begins_xfer;

  //~B6_s1_write_n assignment, which is an e_mux
  assign B6_s1_write_n = ~(cpu_data_master_granted_B6_s1 & cpu_data_master_write);

  assign shifted_address_to_B6_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //B6_s1_address mux, which is an e_mux
  assign B6_s1_address = shifted_address_to_B6_s1_from_cpu_data_master >> 2;

  //d1_B6_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_B6_s1_end_xfer <= 1;
      else if (1)
          d1_B6_s1_end_xfer <= B6_s1_end_xfer;
    end


  //B6_s1_waits_for_read in a cycle, which is an e_mux
  assign B6_s1_waits_for_read = B6_s1_in_a_read_cycle & B6_s1_begins_xfer;

  //B6_s1_in_a_read_cycle assignment, which is an e_assign
  assign B6_s1_in_a_read_cycle = cpu_data_master_granted_B6_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = B6_s1_in_a_read_cycle;

  //B6_s1_waits_for_write in a cycle, which is an e_mux
  assign B6_s1_waits_for_write = B6_s1_in_a_write_cycle & 0;

  //B6_s1_in_a_write_cycle assignment, which is an e_assign
  assign B6_s1_in_a_write_cycle = cpu_data_master_granted_B6_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = B6_s1_in_a_write_cycle;

  assign wait_for_B6_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //B6/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module B7_s1_arbitrator (
                          // inputs:
                           clk,
                           cpu_data_master_address_to_slave,
                           cpu_data_master_read,
                           cpu_data_master_waitrequest,
                           cpu_data_master_write,
                           cpu_data_master_writedata,
                           reset_n,

                          // outputs:
                           B7_s1_address,
                           B7_s1_chipselect,
                           B7_s1_reset_n,
                           B7_s1_write_n,
                           B7_s1_writedata,
                           cpu_data_master_granted_B7_s1,
                           cpu_data_master_qualified_request_B7_s1,
                           cpu_data_master_read_data_valid_B7_s1,
                           cpu_data_master_requests_B7_s1,
                           d1_B7_s1_end_xfer
                        )
;

  output  [  1: 0] B7_s1_address;
  output           B7_s1_chipselect;
  output           B7_s1_reset_n;
  output           B7_s1_write_n;
  output  [ 17: 0] B7_s1_writedata;
  output           cpu_data_master_granted_B7_s1;
  output           cpu_data_master_qualified_request_B7_s1;
  output           cpu_data_master_read_data_valid_B7_s1;
  output           cpu_data_master_requests_B7_s1;
  output           d1_B7_s1_end_xfer;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] B7_s1_address;
  wire             B7_s1_allgrants;
  wire             B7_s1_allow_new_arb_cycle;
  wire             B7_s1_any_bursting_master_saved_grant;
  wire             B7_s1_any_continuerequest;
  wire             B7_s1_arb_counter_enable;
  reg     [  1: 0] B7_s1_arb_share_counter;
  wire    [  1: 0] B7_s1_arb_share_counter_next_value;
  wire    [  1: 0] B7_s1_arb_share_set_values;
  wire             B7_s1_beginbursttransfer_internal;
  wire             B7_s1_begins_xfer;
  wire             B7_s1_chipselect;
  wire             B7_s1_end_xfer;
  wire             B7_s1_firsttransfer;
  wire             B7_s1_grant_vector;
  wire             B7_s1_in_a_read_cycle;
  wire             B7_s1_in_a_write_cycle;
  wire             B7_s1_master_qreq_vector;
  wire             B7_s1_non_bursting_master_requests;
  reg              B7_s1_reg_firsttransfer;
  wire             B7_s1_reset_n;
  reg              B7_s1_slavearbiterlockenable;
  wire             B7_s1_slavearbiterlockenable2;
  wire             B7_s1_unreg_firsttransfer;
  wire             B7_s1_waits_for_read;
  wire             B7_s1_waits_for_write;
  wire             B7_s1_write_n;
  wire    [ 17: 0] B7_s1_writedata;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_B7_s1;
  wire             cpu_data_master_qualified_request_B7_s1;
  wire             cpu_data_master_read_data_valid_B7_s1;
  wire             cpu_data_master_requests_B7_s1;
  wire             cpu_data_master_saved_grant_B7_s1;
  reg              d1_B7_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_B7_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 24: 0] shifted_address_to_B7_s1_from_cpu_data_master;
  wire             wait_for_B7_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~B7_s1_end_xfer;
    end


  assign B7_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_B7_s1));
  assign cpu_data_master_requests_B7_s1 = (({cpu_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h1060) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_write;
  //B7_s1_arb_share_counter set values, which is an e_mux
  assign B7_s1_arb_share_set_values = 1;

  //B7_s1_non_bursting_master_requests mux, which is an e_mux
  assign B7_s1_non_bursting_master_requests = cpu_data_master_requests_B7_s1;

  //B7_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign B7_s1_any_bursting_master_saved_grant = 0;

  //B7_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign B7_s1_arb_share_counter_next_value = B7_s1_firsttransfer ? (B7_s1_arb_share_set_values - 1) : |B7_s1_arb_share_counter ? (B7_s1_arb_share_counter - 1) : 0;

  //B7_s1_allgrants all slave grants, which is an e_mux
  assign B7_s1_allgrants = |B7_s1_grant_vector;

  //B7_s1_end_xfer assignment, which is an e_assign
  assign B7_s1_end_xfer = ~(B7_s1_waits_for_read | B7_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_B7_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_B7_s1 = B7_s1_end_xfer & (~B7_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //B7_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign B7_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_B7_s1 & B7_s1_allgrants) | (end_xfer_arb_share_counter_term_B7_s1 & ~B7_s1_non_bursting_master_requests);

  //B7_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B7_s1_arb_share_counter <= 0;
      else if (B7_s1_arb_counter_enable)
          B7_s1_arb_share_counter <= B7_s1_arb_share_counter_next_value;
    end


  //B7_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B7_s1_slavearbiterlockenable <= 0;
      else if ((|B7_s1_master_qreq_vector & end_xfer_arb_share_counter_term_B7_s1) | (end_xfer_arb_share_counter_term_B7_s1 & ~B7_s1_non_bursting_master_requests))
          B7_s1_slavearbiterlockenable <= |B7_s1_arb_share_counter_next_value;
    end


  //cpu/data_master B7/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = B7_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //B7_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign B7_s1_slavearbiterlockenable2 = |B7_s1_arb_share_counter_next_value;

  //cpu/data_master B7/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = B7_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //B7_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign B7_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_B7_s1 = cpu_data_master_requests_B7_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //B7_s1_writedata mux, which is an e_mux
  assign B7_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_B7_s1 = cpu_data_master_qualified_request_B7_s1;

  //cpu/data_master saved-grant B7/s1, which is an e_assign
  assign cpu_data_master_saved_grant_B7_s1 = cpu_data_master_requests_B7_s1;

  //allow new arb cycle for B7/s1, which is an e_assign
  assign B7_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign B7_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign B7_s1_master_qreq_vector = 1;

  //B7_s1_reset_n assignment, which is an e_assign
  assign B7_s1_reset_n = reset_n;

  assign B7_s1_chipselect = cpu_data_master_granted_B7_s1;
  //B7_s1_firsttransfer first transaction, which is an e_assign
  assign B7_s1_firsttransfer = B7_s1_begins_xfer ? B7_s1_unreg_firsttransfer : B7_s1_reg_firsttransfer;

  //B7_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign B7_s1_unreg_firsttransfer = ~(B7_s1_slavearbiterlockenable & B7_s1_any_continuerequest);

  //B7_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B7_s1_reg_firsttransfer <= 1'b1;
      else if (B7_s1_begins_xfer)
          B7_s1_reg_firsttransfer <= B7_s1_unreg_firsttransfer;
    end


  //B7_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign B7_s1_beginbursttransfer_internal = B7_s1_begins_xfer;

  //~B7_s1_write_n assignment, which is an e_mux
  assign B7_s1_write_n = ~(cpu_data_master_granted_B7_s1 & cpu_data_master_write);

  assign shifted_address_to_B7_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //B7_s1_address mux, which is an e_mux
  assign B7_s1_address = shifted_address_to_B7_s1_from_cpu_data_master >> 2;

  //d1_B7_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_B7_s1_end_xfer <= 1;
      else if (1)
          d1_B7_s1_end_xfer <= B7_s1_end_xfer;
    end


  //B7_s1_waits_for_read in a cycle, which is an e_mux
  assign B7_s1_waits_for_read = B7_s1_in_a_read_cycle & B7_s1_begins_xfer;

  //B7_s1_in_a_read_cycle assignment, which is an e_assign
  assign B7_s1_in_a_read_cycle = cpu_data_master_granted_B7_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = B7_s1_in_a_read_cycle;

  //B7_s1_waits_for_write in a cycle, which is an e_mux
  assign B7_s1_waits_for_write = B7_s1_in_a_write_cycle & 0;

  //B7_s1_in_a_write_cycle assignment, which is an e_assign
  assign B7_s1_in_a_write_cycle = cpu_data_master_granted_B7_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = B7_s1_in_a_write_cycle;

  assign wait_for_B7_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //B7/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module B8_s1_arbitrator (
                          // inputs:
                           clk,
                           cpu_data_master_address_to_slave,
                           cpu_data_master_read,
                           cpu_data_master_waitrequest,
                           cpu_data_master_write,
                           cpu_data_master_writedata,
                           reset_n,

                          // outputs:
                           B8_s1_address,
                           B8_s1_chipselect,
                           B8_s1_reset_n,
                           B8_s1_write_n,
                           B8_s1_writedata,
                           cpu_data_master_granted_B8_s1,
                           cpu_data_master_qualified_request_B8_s1,
                           cpu_data_master_read_data_valid_B8_s1,
                           cpu_data_master_requests_B8_s1,
                           d1_B8_s1_end_xfer
                        )
;

  output  [  1: 0] B8_s1_address;
  output           B8_s1_chipselect;
  output           B8_s1_reset_n;
  output           B8_s1_write_n;
  output  [ 17: 0] B8_s1_writedata;
  output           cpu_data_master_granted_B8_s1;
  output           cpu_data_master_qualified_request_B8_s1;
  output           cpu_data_master_read_data_valid_B8_s1;
  output           cpu_data_master_requests_B8_s1;
  output           d1_B8_s1_end_xfer;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] B8_s1_address;
  wire             B8_s1_allgrants;
  wire             B8_s1_allow_new_arb_cycle;
  wire             B8_s1_any_bursting_master_saved_grant;
  wire             B8_s1_any_continuerequest;
  wire             B8_s1_arb_counter_enable;
  reg     [  1: 0] B8_s1_arb_share_counter;
  wire    [  1: 0] B8_s1_arb_share_counter_next_value;
  wire    [  1: 0] B8_s1_arb_share_set_values;
  wire             B8_s1_beginbursttransfer_internal;
  wire             B8_s1_begins_xfer;
  wire             B8_s1_chipselect;
  wire             B8_s1_end_xfer;
  wire             B8_s1_firsttransfer;
  wire             B8_s1_grant_vector;
  wire             B8_s1_in_a_read_cycle;
  wire             B8_s1_in_a_write_cycle;
  wire             B8_s1_master_qreq_vector;
  wire             B8_s1_non_bursting_master_requests;
  reg              B8_s1_reg_firsttransfer;
  wire             B8_s1_reset_n;
  reg              B8_s1_slavearbiterlockenable;
  wire             B8_s1_slavearbiterlockenable2;
  wire             B8_s1_unreg_firsttransfer;
  wire             B8_s1_waits_for_read;
  wire             B8_s1_waits_for_write;
  wire             B8_s1_write_n;
  wire    [ 17: 0] B8_s1_writedata;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_B8_s1;
  wire             cpu_data_master_qualified_request_B8_s1;
  wire             cpu_data_master_read_data_valid_B8_s1;
  wire             cpu_data_master_requests_B8_s1;
  wire             cpu_data_master_saved_grant_B8_s1;
  reg              d1_B8_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_B8_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 24: 0] shifted_address_to_B8_s1_from_cpu_data_master;
  wire             wait_for_B8_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~B8_s1_end_xfer;
    end


  assign B8_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_B8_s1));
  assign cpu_data_master_requests_B8_s1 = (({cpu_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h1070) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_write;
  //B8_s1_arb_share_counter set values, which is an e_mux
  assign B8_s1_arb_share_set_values = 1;

  //B8_s1_non_bursting_master_requests mux, which is an e_mux
  assign B8_s1_non_bursting_master_requests = cpu_data_master_requests_B8_s1;

  //B8_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign B8_s1_any_bursting_master_saved_grant = 0;

  //B8_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign B8_s1_arb_share_counter_next_value = B8_s1_firsttransfer ? (B8_s1_arb_share_set_values - 1) : |B8_s1_arb_share_counter ? (B8_s1_arb_share_counter - 1) : 0;

  //B8_s1_allgrants all slave grants, which is an e_mux
  assign B8_s1_allgrants = |B8_s1_grant_vector;

  //B8_s1_end_xfer assignment, which is an e_assign
  assign B8_s1_end_xfer = ~(B8_s1_waits_for_read | B8_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_B8_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_B8_s1 = B8_s1_end_xfer & (~B8_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //B8_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign B8_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_B8_s1 & B8_s1_allgrants) | (end_xfer_arb_share_counter_term_B8_s1 & ~B8_s1_non_bursting_master_requests);

  //B8_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B8_s1_arb_share_counter <= 0;
      else if (B8_s1_arb_counter_enable)
          B8_s1_arb_share_counter <= B8_s1_arb_share_counter_next_value;
    end


  //B8_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B8_s1_slavearbiterlockenable <= 0;
      else if ((|B8_s1_master_qreq_vector & end_xfer_arb_share_counter_term_B8_s1) | (end_xfer_arb_share_counter_term_B8_s1 & ~B8_s1_non_bursting_master_requests))
          B8_s1_slavearbiterlockenable <= |B8_s1_arb_share_counter_next_value;
    end


  //cpu/data_master B8/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = B8_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //B8_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign B8_s1_slavearbiterlockenable2 = |B8_s1_arb_share_counter_next_value;

  //cpu/data_master B8/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = B8_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //B8_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign B8_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_B8_s1 = cpu_data_master_requests_B8_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //B8_s1_writedata mux, which is an e_mux
  assign B8_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_B8_s1 = cpu_data_master_qualified_request_B8_s1;

  //cpu/data_master saved-grant B8/s1, which is an e_assign
  assign cpu_data_master_saved_grant_B8_s1 = cpu_data_master_requests_B8_s1;

  //allow new arb cycle for B8/s1, which is an e_assign
  assign B8_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign B8_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign B8_s1_master_qreq_vector = 1;

  //B8_s1_reset_n assignment, which is an e_assign
  assign B8_s1_reset_n = reset_n;

  assign B8_s1_chipselect = cpu_data_master_granted_B8_s1;
  //B8_s1_firsttransfer first transaction, which is an e_assign
  assign B8_s1_firsttransfer = B8_s1_begins_xfer ? B8_s1_unreg_firsttransfer : B8_s1_reg_firsttransfer;

  //B8_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign B8_s1_unreg_firsttransfer = ~(B8_s1_slavearbiterlockenable & B8_s1_any_continuerequest);

  //B8_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          B8_s1_reg_firsttransfer <= 1'b1;
      else if (B8_s1_begins_xfer)
          B8_s1_reg_firsttransfer <= B8_s1_unreg_firsttransfer;
    end


  //B8_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign B8_s1_beginbursttransfer_internal = B8_s1_begins_xfer;

  //~B8_s1_write_n assignment, which is an e_mux
  assign B8_s1_write_n = ~(cpu_data_master_granted_B8_s1 & cpu_data_master_write);

  assign shifted_address_to_B8_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //B8_s1_address mux, which is an e_mux
  assign B8_s1_address = shifted_address_to_B8_s1_from_cpu_data_master >> 2;

  //d1_B8_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_B8_s1_end_xfer <= 1;
      else if (1)
          d1_B8_s1_end_xfer <= B8_s1_end_xfer;
    end


  //B8_s1_waits_for_read in a cycle, which is an e_mux
  assign B8_s1_waits_for_read = B8_s1_in_a_read_cycle & B8_s1_begins_xfer;

  //B8_s1_in_a_read_cycle assignment, which is an e_assign
  assign B8_s1_in_a_read_cycle = cpu_data_master_granted_B8_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = B8_s1_in_a_read_cycle;

  //B8_s1_waits_for_write in a cycle, which is an e_mux
  assign B8_s1_waits_for_write = B8_s1_in_a_write_cycle & 0;

  //B8_s1_in_a_write_cycle assignment, which is an e_assign
  assign B8_s1_in_a_write_cycle = cpu_data_master_granted_B8_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = B8_s1_in_a_write_cycle;

  assign wait_for_B8_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //B8/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module RESET_s1_arbitrator (
                             // inputs:
                              RESET_s1_readdata,
                              clk,
                              cpu_data_master_address_to_slave,
                              cpu_data_master_read,
                              cpu_data_master_write,
                              reset_n,

                             // outputs:
                              RESET_s1_address,
                              RESET_s1_readdata_from_sa,
                              RESET_s1_reset_n,
                              cpu_data_master_granted_RESET_s1,
                              cpu_data_master_qualified_request_RESET_s1,
                              cpu_data_master_read_data_valid_RESET_s1,
                              cpu_data_master_requests_RESET_s1,
                              d1_RESET_s1_end_xfer
                           )
;

  output  [  1: 0] RESET_s1_address;
  output           RESET_s1_readdata_from_sa;
  output           RESET_s1_reset_n;
  output           cpu_data_master_granted_RESET_s1;
  output           cpu_data_master_qualified_request_RESET_s1;
  output           cpu_data_master_read_data_valid_RESET_s1;
  output           cpu_data_master_requests_RESET_s1;
  output           d1_RESET_s1_end_xfer;
  input            RESET_s1_readdata;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_write;
  input            reset_n;

  wire    [  1: 0] RESET_s1_address;
  wire             RESET_s1_allgrants;
  wire             RESET_s1_allow_new_arb_cycle;
  wire             RESET_s1_any_bursting_master_saved_grant;
  wire             RESET_s1_any_continuerequest;
  wire             RESET_s1_arb_counter_enable;
  reg     [  1: 0] RESET_s1_arb_share_counter;
  wire    [  1: 0] RESET_s1_arb_share_counter_next_value;
  wire    [  1: 0] RESET_s1_arb_share_set_values;
  wire             RESET_s1_beginbursttransfer_internal;
  wire             RESET_s1_begins_xfer;
  wire             RESET_s1_end_xfer;
  wire             RESET_s1_firsttransfer;
  wire             RESET_s1_grant_vector;
  wire             RESET_s1_in_a_read_cycle;
  wire             RESET_s1_in_a_write_cycle;
  wire             RESET_s1_master_qreq_vector;
  wire             RESET_s1_non_bursting_master_requests;
  wire             RESET_s1_readdata_from_sa;
  reg              RESET_s1_reg_firsttransfer;
  wire             RESET_s1_reset_n;
  reg              RESET_s1_slavearbiterlockenable;
  wire             RESET_s1_slavearbiterlockenable2;
  wire             RESET_s1_unreg_firsttransfer;
  wire             RESET_s1_waits_for_read;
  wire             RESET_s1_waits_for_write;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_RESET_s1;
  wire             cpu_data_master_qualified_request_RESET_s1;
  wire             cpu_data_master_read_data_valid_RESET_s1;
  wire             cpu_data_master_requests_RESET_s1;
  wire             cpu_data_master_saved_grant_RESET_s1;
  reg              d1_RESET_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_RESET_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 24: 0] shifted_address_to_RESET_s1_from_cpu_data_master;
  wire             wait_for_RESET_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~RESET_s1_end_xfer;
    end


  assign RESET_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_RESET_s1));
  //assign RESET_s1_readdata_from_sa = RESET_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign RESET_s1_readdata_from_sa = RESET_s1_readdata;

  assign cpu_data_master_requests_RESET_s1 = (({cpu_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h10a0) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_read;
  //RESET_s1_arb_share_counter set values, which is an e_mux
  assign RESET_s1_arb_share_set_values = 1;

  //RESET_s1_non_bursting_master_requests mux, which is an e_mux
  assign RESET_s1_non_bursting_master_requests = cpu_data_master_requests_RESET_s1;

  //RESET_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign RESET_s1_any_bursting_master_saved_grant = 0;

  //RESET_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign RESET_s1_arb_share_counter_next_value = RESET_s1_firsttransfer ? (RESET_s1_arb_share_set_values - 1) : |RESET_s1_arb_share_counter ? (RESET_s1_arb_share_counter - 1) : 0;

  //RESET_s1_allgrants all slave grants, which is an e_mux
  assign RESET_s1_allgrants = |RESET_s1_grant_vector;

  //RESET_s1_end_xfer assignment, which is an e_assign
  assign RESET_s1_end_xfer = ~(RESET_s1_waits_for_read | RESET_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_RESET_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_RESET_s1 = RESET_s1_end_xfer & (~RESET_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //RESET_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign RESET_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_RESET_s1 & RESET_s1_allgrants) | (end_xfer_arb_share_counter_term_RESET_s1 & ~RESET_s1_non_bursting_master_requests);

  //RESET_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          RESET_s1_arb_share_counter <= 0;
      else if (RESET_s1_arb_counter_enable)
          RESET_s1_arb_share_counter <= RESET_s1_arb_share_counter_next_value;
    end


  //RESET_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          RESET_s1_slavearbiterlockenable <= 0;
      else if ((|RESET_s1_master_qreq_vector & end_xfer_arb_share_counter_term_RESET_s1) | (end_xfer_arb_share_counter_term_RESET_s1 & ~RESET_s1_non_bursting_master_requests))
          RESET_s1_slavearbiterlockenable <= |RESET_s1_arb_share_counter_next_value;
    end


  //cpu/data_master RESET/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = RESET_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //RESET_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign RESET_s1_slavearbiterlockenable2 = |RESET_s1_arb_share_counter_next_value;

  //cpu/data_master RESET/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = RESET_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //RESET_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign RESET_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_RESET_s1 = cpu_data_master_requests_RESET_s1;
  //master is always granted when requested
  assign cpu_data_master_granted_RESET_s1 = cpu_data_master_qualified_request_RESET_s1;

  //cpu/data_master saved-grant RESET/s1, which is an e_assign
  assign cpu_data_master_saved_grant_RESET_s1 = cpu_data_master_requests_RESET_s1;

  //allow new arb cycle for RESET/s1, which is an e_assign
  assign RESET_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign RESET_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign RESET_s1_master_qreq_vector = 1;

  //RESET_s1_reset_n assignment, which is an e_assign
  assign RESET_s1_reset_n = reset_n;

  //RESET_s1_firsttransfer first transaction, which is an e_assign
  assign RESET_s1_firsttransfer = RESET_s1_begins_xfer ? RESET_s1_unreg_firsttransfer : RESET_s1_reg_firsttransfer;

  //RESET_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign RESET_s1_unreg_firsttransfer = ~(RESET_s1_slavearbiterlockenable & RESET_s1_any_continuerequest);

  //RESET_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          RESET_s1_reg_firsttransfer <= 1'b1;
      else if (RESET_s1_begins_xfer)
          RESET_s1_reg_firsttransfer <= RESET_s1_unreg_firsttransfer;
    end


  //RESET_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign RESET_s1_beginbursttransfer_internal = RESET_s1_begins_xfer;

  assign shifted_address_to_RESET_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //RESET_s1_address mux, which is an e_mux
  assign RESET_s1_address = shifted_address_to_RESET_s1_from_cpu_data_master >> 2;

  //d1_RESET_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_RESET_s1_end_xfer <= 1;
      else if (1)
          d1_RESET_s1_end_xfer <= RESET_s1_end_xfer;
    end


  //RESET_s1_waits_for_read in a cycle, which is an e_mux
  assign RESET_s1_waits_for_read = RESET_s1_in_a_read_cycle & RESET_s1_begins_xfer;

  //RESET_s1_in_a_read_cycle assignment, which is an e_assign
  assign RESET_s1_in_a_read_cycle = cpu_data_master_granted_RESET_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = RESET_s1_in_a_read_cycle;

  //RESET_s1_waits_for_write in a cycle, which is an e_mux
  assign RESET_s1_waits_for_write = RESET_s1_in_a_write_cycle & 0;

  //RESET_s1_in_a_write_cycle assignment, which is an e_assign
  assign RESET_s1_in_a_write_cycle = cpu_data_master_granted_RESET_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = RESET_s1_in_a_write_cycle;

  assign wait_for_RESET_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //RESET/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module XOFF_s1_arbitrator (
                            // inputs:
                             XOFF_s1_readdata,
                             clk,
                             cpu_data_master_address_to_slave,
                             cpu_data_master_read,
                             cpu_data_master_write,
                             reset_n,

                            // outputs:
                             XOFF_s1_address,
                             XOFF_s1_readdata_from_sa,
                             XOFF_s1_reset_n,
                             cpu_data_master_granted_XOFF_s1,
                             cpu_data_master_qualified_request_XOFF_s1,
                             cpu_data_master_read_data_valid_XOFF_s1,
                             cpu_data_master_requests_XOFF_s1,
                             d1_XOFF_s1_end_xfer
                          )
;

  output  [  1: 0] XOFF_s1_address;
  output  [  8: 0] XOFF_s1_readdata_from_sa;
  output           XOFF_s1_reset_n;
  output           cpu_data_master_granted_XOFF_s1;
  output           cpu_data_master_qualified_request_XOFF_s1;
  output           cpu_data_master_read_data_valid_XOFF_s1;
  output           cpu_data_master_requests_XOFF_s1;
  output           d1_XOFF_s1_end_xfer;
  input   [  8: 0] XOFF_s1_readdata;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_write;
  input            reset_n;

  wire    [  1: 0] XOFF_s1_address;
  wire             XOFF_s1_allgrants;
  wire             XOFF_s1_allow_new_arb_cycle;
  wire             XOFF_s1_any_bursting_master_saved_grant;
  wire             XOFF_s1_any_continuerequest;
  wire             XOFF_s1_arb_counter_enable;
  reg     [  1: 0] XOFF_s1_arb_share_counter;
  wire    [  1: 0] XOFF_s1_arb_share_counter_next_value;
  wire    [  1: 0] XOFF_s1_arb_share_set_values;
  wire             XOFF_s1_beginbursttransfer_internal;
  wire             XOFF_s1_begins_xfer;
  wire             XOFF_s1_end_xfer;
  wire             XOFF_s1_firsttransfer;
  wire             XOFF_s1_grant_vector;
  wire             XOFF_s1_in_a_read_cycle;
  wire             XOFF_s1_in_a_write_cycle;
  wire             XOFF_s1_master_qreq_vector;
  wire             XOFF_s1_non_bursting_master_requests;
  wire    [  8: 0] XOFF_s1_readdata_from_sa;
  reg              XOFF_s1_reg_firsttransfer;
  wire             XOFF_s1_reset_n;
  reg              XOFF_s1_slavearbiterlockenable;
  wire             XOFF_s1_slavearbiterlockenable2;
  wire             XOFF_s1_unreg_firsttransfer;
  wire             XOFF_s1_waits_for_read;
  wire             XOFF_s1_waits_for_write;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_XOFF_s1;
  wire             cpu_data_master_qualified_request_XOFF_s1;
  wire             cpu_data_master_read_data_valid_XOFF_s1;
  wire             cpu_data_master_requests_XOFF_s1;
  wire             cpu_data_master_saved_grant_XOFF_s1;
  reg              d1_XOFF_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_XOFF_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 24: 0] shifted_address_to_XOFF_s1_from_cpu_data_master;
  wire             wait_for_XOFF_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~XOFF_s1_end_xfer;
    end


  assign XOFF_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_XOFF_s1));
  //assign XOFF_s1_readdata_from_sa = XOFF_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign XOFF_s1_readdata_from_sa = XOFF_s1_readdata;

  assign cpu_data_master_requests_XOFF_s1 = (({cpu_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h10b0) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_read;
  //XOFF_s1_arb_share_counter set values, which is an e_mux
  assign XOFF_s1_arb_share_set_values = 1;

  //XOFF_s1_non_bursting_master_requests mux, which is an e_mux
  assign XOFF_s1_non_bursting_master_requests = cpu_data_master_requests_XOFF_s1;

  //XOFF_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign XOFF_s1_any_bursting_master_saved_grant = 0;

  //XOFF_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign XOFF_s1_arb_share_counter_next_value = XOFF_s1_firsttransfer ? (XOFF_s1_arb_share_set_values - 1) : |XOFF_s1_arb_share_counter ? (XOFF_s1_arb_share_counter - 1) : 0;

  //XOFF_s1_allgrants all slave grants, which is an e_mux
  assign XOFF_s1_allgrants = |XOFF_s1_grant_vector;

  //XOFF_s1_end_xfer assignment, which is an e_assign
  assign XOFF_s1_end_xfer = ~(XOFF_s1_waits_for_read | XOFF_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_XOFF_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_XOFF_s1 = XOFF_s1_end_xfer & (~XOFF_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //XOFF_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign XOFF_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_XOFF_s1 & XOFF_s1_allgrants) | (end_xfer_arb_share_counter_term_XOFF_s1 & ~XOFF_s1_non_bursting_master_requests);

  //XOFF_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          XOFF_s1_arb_share_counter <= 0;
      else if (XOFF_s1_arb_counter_enable)
          XOFF_s1_arb_share_counter <= XOFF_s1_arb_share_counter_next_value;
    end


  //XOFF_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          XOFF_s1_slavearbiterlockenable <= 0;
      else if ((|XOFF_s1_master_qreq_vector & end_xfer_arb_share_counter_term_XOFF_s1) | (end_xfer_arb_share_counter_term_XOFF_s1 & ~XOFF_s1_non_bursting_master_requests))
          XOFF_s1_slavearbiterlockenable <= |XOFF_s1_arb_share_counter_next_value;
    end


  //cpu/data_master XOFF/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = XOFF_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //XOFF_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign XOFF_s1_slavearbiterlockenable2 = |XOFF_s1_arb_share_counter_next_value;

  //cpu/data_master XOFF/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = XOFF_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //XOFF_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign XOFF_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_XOFF_s1 = cpu_data_master_requests_XOFF_s1;
  //master is always granted when requested
  assign cpu_data_master_granted_XOFF_s1 = cpu_data_master_qualified_request_XOFF_s1;

  //cpu/data_master saved-grant XOFF/s1, which is an e_assign
  assign cpu_data_master_saved_grant_XOFF_s1 = cpu_data_master_requests_XOFF_s1;

  //allow new arb cycle for XOFF/s1, which is an e_assign
  assign XOFF_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign XOFF_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign XOFF_s1_master_qreq_vector = 1;

  //XOFF_s1_reset_n assignment, which is an e_assign
  assign XOFF_s1_reset_n = reset_n;

  //XOFF_s1_firsttransfer first transaction, which is an e_assign
  assign XOFF_s1_firsttransfer = XOFF_s1_begins_xfer ? XOFF_s1_unreg_firsttransfer : XOFF_s1_reg_firsttransfer;

  //XOFF_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign XOFF_s1_unreg_firsttransfer = ~(XOFF_s1_slavearbiterlockenable & XOFF_s1_any_continuerequest);

  //XOFF_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          XOFF_s1_reg_firsttransfer <= 1'b1;
      else if (XOFF_s1_begins_xfer)
          XOFF_s1_reg_firsttransfer <= XOFF_s1_unreg_firsttransfer;
    end


  //XOFF_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign XOFF_s1_beginbursttransfer_internal = XOFF_s1_begins_xfer;

  assign shifted_address_to_XOFF_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //XOFF_s1_address mux, which is an e_mux
  assign XOFF_s1_address = shifted_address_to_XOFF_s1_from_cpu_data_master >> 2;

  //d1_XOFF_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_XOFF_s1_end_xfer <= 1;
      else if (1)
          d1_XOFF_s1_end_xfer <= XOFF_s1_end_xfer;
    end


  //XOFF_s1_waits_for_read in a cycle, which is an e_mux
  assign XOFF_s1_waits_for_read = XOFF_s1_in_a_read_cycle & XOFF_s1_begins_xfer;

  //XOFF_s1_in_a_read_cycle assignment, which is an e_assign
  assign XOFF_s1_in_a_read_cycle = cpu_data_master_granted_XOFF_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = XOFF_s1_in_a_read_cycle;

  //XOFF_s1_waits_for_write in a cycle, which is an e_mux
  assign XOFF_s1_waits_for_write = XOFF_s1_in_a_write_cycle & 0;

  //XOFF_s1_in_a_write_cycle assignment, which is an e_assign
  assign XOFF_s1_in_a_write_cycle = cpu_data_master_granted_XOFF_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = XOFF_s1_in_a_write_cycle;

  assign wait_for_XOFF_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //XOFF/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module YOFF_s1_arbitrator (
                            // inputs:
                             YOFF_s1_readdata,
                             clk,
                             cpu_data_master_address_to_slave,
                             cpu_data_master_read,
                             cpu_data_master_write,
                             reset_n,

                            // outputs:
                             YOFF_s1_address,
                             YOFF_s1_readdata_from_sa,
                             YOFF_s1_reset_n,
                             cpu_data_master_granted_YOFF_s1,
                             cpu_data_master_qualified_request_YOFF_s1,
                             cpu_data_master_read_data_valid_YOFF_s1,
                             cpu_data_master_requests_YOFF_s1,
                             d1_YOFF_s1_end_xfer
                          )
;

  output  [  1: 0] YOFF_s1_address;
  output  [  8: 0] YOFF_s1_readdata_from_sa;
  output           YOFF_s1_reset_n;
  output           cpu_data_master_granted_YOFF_s1;
  output           cpu_data_master_qualified_request_YOFF_s1;
  output           cpu_data_master_read_data_valid_YOFF_s1;
  output           cpu_data_master_requests_YOFF_s1;
  output           d1_YOFF_s1_end_xfer;
  input   [  8: 0] YOFF_s1_readdata;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_write;
  input            reset_n;

  wire    [  1: 0] YOFF_s1_address;
  wire             YOFF_s1_allgrants;
  wire             YOFF_s1_allow_new_arb_cycle;
  wire             YOFF_s1_any_bursting_master_saved_grant;
  wire             YOFF_s1_any_continuerequest;
  wire             YOFF_s1_arb_counter_enable;
  reg     [  1: 0] YOFF_s1_arb_share_counter;
  wire    [  1: 0] YOFF_s1_arb_share_counter_next_value;
  wire    [  1: 0] YOFF_s1_arb_share_set_values;
  wire             YOFF_s1_beginbursttransfer_internal;
  wire             YOFF_s1_begins_xfer;
  wire             YOFF_s1_end_xfer;
  wire             YOFF_s1_firsttransfer;
  wire             YOFF_s1_grant_vector;
  wire             YOFF_s1_in_a_read_cycle;
  wire             YOFF_s1_in_a_write_cycle;
  wire             YOFF_s1_master_qreq_vector;
  wire             YOFF_s1_non_bursting_master_requests;
  wire    [  8: 0] YOFF_s1_readdata_from_sa;
  reg              YOFF_s1_reg_firsttransfer;
  wire             YOFF_s1_reset_n;
  reg              YOFF_s1_slavearbiterlockenable;
  wire             YOFF_s1_slavearbiterlockenable2;
  wire             YOFF_s1_unreg_firsttransfer;
  wire             YOFF_s1_waits_for_read;
  wire             YOFF_s1_waits_for_write;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_YOFF_s1;
  wire             cpu_data_master_qualified_request_YOFF_s1;
  wire             cpu_data_master_read_data_valid_YOFF_s1;
  wire             cpu_data_master_requests_YOFF_s1;
  wire             cpu_data_master_saved_grant_YOFF_s1;
  reg              d1_YOFF_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_YOFF_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 24: 0] shifted_address_to_YOFF_s1_from_cpu_data_master;
  wire             wait_for_YOFF_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~YOFF_s1_end_xfer;
    end


  assign YOFF_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_YOFF_s1));
  //assign YOFF_s1_readdata_from_sa = YOFF_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign YOFF_s1_readdata_from_sa = YOFF_s1_readdata;

  assign cpu_data_master_requests_YOFF_s1 = (({cpu_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h10c0) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_read;
  //YOFF_s1_arb_share_counter set values, which is an e_mux
  assign YOFF_s1_arb_share_set_values = 1;

  //YOFF_s1_non_bursting_master_requests mux, which is an e_mux
  assign YOFF_s1_non_bursting_master_requests = cpu_data_master_requests_YOFF_s1;

  //YOFF_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign YOFF_s1_any_bursting_master_saved_grant = 0;

  //YOFF_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign YOFF_s1_arb_share_counter_next_value = YOFF_s1_firsttransfer ? (YOFF_s1_arb_share_set_values - 1) : |YOFF_s1_arb_share_counter ? (YOFF_s1_arb_share_counter - 1) : 0;

  //YOFF_s1_allgrants all slave grants, which is an e_mux
  assign YOFF_s1_allgrants = |YOFF_s1_grant_vector;

  //YOFF_s1_end_xfer assignment, which is an e_assign
  assign YOFF_s1_end_xfer = ~(YOFF_s1_waits_for_read | YOFF_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_YOFF_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_YOFF_s1 = YOFF_s1_end_xfer & (~YOFF_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //YOFF_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign YOFF_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_YOFF_s1 & YOFF_s1_allgrants) | (end_xfer_arb_share_counter_term_YOFF_s1 & ~YOFF_s1_non_bursting_master_requests);

  //YOFF_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          YOFF_s1_arb_share_counter <= 0;
      else if (YOFF_s1_arb_counter_enable)
          YOFF_s1_arb_share_counter <= YOFF_s1_arb_share_counter_next_value;
    end


  //YOFF_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          YOFF_s1_slavearbiterlockenable <= 0;
      else if ((|YOFF_s1_master_qreq_vector & end_xfer_arb_share_counter_term_YOFF_s1) | (end_xfer_arb_share_counter_term_YOFF_s1 & ~YOFF_s1_non_bursting_master_requests))
          YOFF_s1_slavearbiterlockenable <= |YOFF_s1_arb_share_counter_next_value;
    end


  //cpu/data_master YOFF/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = YOFF_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //YOFF_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign YOFF_s1_slavearbiterlockenable2 = |YOFF_s1_arb_share_counter_next_value;

  //cpu/data_master YOFF/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = YOFF_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //YOFF_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign YOFF_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_YOFF_s1 = cpu_data_master_requests_YOFF_s1;
  //master is always granted when requested
  assign cpu_data_master_granted_YOFF_s1 = cpu_data_master_qualified_request_YOFF_s1;

  //cpu/data_master saved-grant YOFF/s1, which is an e_assign
  assign cpu_data_master_saved_grant_YOFF_s1 = cpu_data_master_requests_YOFF_s1;

  //allow new arb cycle for YOFF/s1, which is an e_assign
  assign YOFF_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign YOFF_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign YOFF_s1_master_qreq_vector = 1;

  //YOFF_s1_reset_n assignment, which is an e_assign
  assign YOFF_s1_reset_n = reset_n;

  //YOFF_s1_firsttransfer first transaction, which is an e_assign
  assign YOFF_s1_firsttransfer = YOFF_s1_begins_xfer ? YOFF_s1_unreg_firsttransfer : YOFF_s1_reg_firsttransfer;

  //YOFF_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign YOFF_s1_unreg_firsttransfer = ~(YOFF_s1_slavearbiterlockenable & YOFF_s1_any_continuerequest);

  //YOFF_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          YOFF_s1_reg_firsttransfer <= 1'b1;
      else if (YOFF_s1_begins_xfer)
          YOFF_s1_reg_firsttransfer <= YOFF_s1_unreg_firsttransfer;
    end


  //YOFF_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign YOFF_s1_beginbursttransfer_internal = YOFF_s1_begins_xfer;

  assign shifted_address_to_YOFF_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //YOFF_s1_address mux, which is an e_mux
  assign YOFF_s1_address = shifted_address_to_YOFF_s1_from_cpu_data_master >> 2;

  //d1_YOFF_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_YOFF_s1_end_xfer <= 1;
      else if (1)
          d1_YOFF_s1_end_xfer <= YOFF_s1_end_xfer;
    end


  //YOFF_s1_waits_for_read in a cycle, which is an e_mux
  assign YOFF_s1_waits_for_read = YOFF_s1_in_a_read_cycle & YOFF_s1_begins_xfer;

  //YOFF_s1_in_a_read_cycle assignment, which is an e_assign
  assign YOFF_s1_in_a_read_cycle = cpu_data_master_granted_YOFF_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = YOFF_s1_in_a_read_cycle;

  //YOFF_s1_waits_for_write in a cycle, which is an e_mux
  assign YOFF_s1_waits_for_write = YOFF_s1_in_a_write_cycle & 0;

  //YOFF_s1_in_a_write_cycle assignment, which is an e_assign
  assign YOFF_s1_in_a_write_cycle = cpu_data_master_granted_YOFF_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = YOFF_s1_in_a_write_cycle;

  assign wait_for_YOFF_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //YOFF/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_jtag_debug_module_arbitrator (
                                          // inputs:
                                           clk,
                                           cpu_data_master_address_to_slave,
                                           cpu_data_master_byteenable,
                                           cpu_data_master_debugaccess,
                                           cpu_data_master_read,
                                           cpu_data_master_waitrequest,
                                           cpu_data_master_write,
                                           cpu_data_master_writedata,
                                           cpu_instruction_master_address_to_slave,
                                           cpu_instruction_master_latency_counter,
                                           cpu_instruction_master_read,
                                           cpu_jtag_debug_module_readdata,
                                           cpu_jtag_debug_module_resetrequest,
                                           reset_n,

                                          // outputs:
                                           cpu_data_master_granted_cpu_jtag_debug_module,
                                           cpu_data_master_qualified_request_cpu_jtag_debug_module,
                                           cpu_data_master_read_data_valid_cpu_jtag_debug_module,
                                           cpu_data_master_requests_cpu_jtag_debug_module,
                                           cpu_instruction_master_granted_cpu_jtag_debug_module,
                                           cpu_instruction_master_qualified_request_cpu_jtag_debug_module,
                                           cpu_instruction_master_read_data_valid_cpu_jtag_debug_module,
                                           cpu_instruction_master_requests_cpu_jtag_debug_module,
                                           cpu_jtag_debug_module_address,
                                           cpu_jtag_debug_module_begintransfer,
                                           cpu_jtag_debug_module_byteenable,
                                           cpu_jtag_debug_module_chipselect,
                                           cpu_jtag_debug_module_debugaccess,
                                           cpu_jtag_debug_module_readdata_from_sa,
                                           cpu_jtag_debug_module_reset,
                                           cpu_jtag_debug_module_resetrequest_from_sa,
                                           cpu_jtag_debug_module_write,
                                           cpu_jtag_debug_module_writedata,
                                           d1_cpu_jtag_debug_module_end_xfer
                                        )
;

  output           cpu_data_master_granted_cpu_jtag_debug_module;
  output           cpu_data_master_qualified_request_cpu_jtag_debug_module;
  output           cpu_data_master_read_data_valid_cpu_jtag_debug_module;
  output           cpu_data_master_requests_cpu_jtag_debug_module;
  output           cpu_instruction_master_granted_cpu_jtag_debug_module;
  output           cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
  output           cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
  output           cpu_instruction_master_requests_cpu_jtag_debug_module;
  output  [  8: 0] cpu_jtag_debug_module_address;
  output           cpu_jtag_debug_module_begintransfer;
  output  [  3: 0] cpu_jtag_debug_module_byteenable;
  output           cpu_jtag_debug_module_chipselect;
  output           cpu_jtag_debug_module_debugaccess;
  output  [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
  output           cpu_jtag_debug_module_reset;
  output           cpu_jtag_debug_module_resetrequest_from_sa;
  output           cpu_jtag_debug_module_write;
  output  [ 31: 0] cpu_jtag_debug_module_writedata;
  output           d1_cpu_jtag_debug_module_end_xfer;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input   [  3: 0] cpu_data_master_byteenable;
  input            cpu_data_master_debugaccess;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input   [ 24: 0] cpu_instruction_master_address_to_slave;
  input            cpu_instruction_master_latency_counter;
  input            cpu_instruction_master_read;
  input   [ 31: 0] cpu_jtag_debug_module_readdata;
  input            cpu_jtag_debug_module_resetrequest;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_cpu_jtag_debug_module;
  wire             cpu_data_master_qualified_request_cpu_jtag_debug_module;
  wire             cpu_data_master_read_data_valid_cpu_jtag_debug_module;
  wire             cpu_data_master_requests_cpu_jtag_debug_module;
  wire             cpu_data_master_saved_grant_cpu_jtag_debug_module;
  wire             cpu_instruction_master_arbiterlock;
  wire             cpu_instruction_master_arbiterlock2;
  wire             cpu_instruction_master_continuerequest;
  wire             cpu_instruction_master_granted_cpu_jtag_debug_module;
  wire             cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
  wire             cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
  wire             cpu_instruction_master_requests_cpu_jtag_debug_module;
  wire             cpu_instruction_master_saved_grant_cpu_jtag_debug_module;
  wire    [  8: 0] cpu_jtag_debug_module_address;
  wire             cpu_jtag_debug_module_allgrants;
  wire             cpu_jtag_debug_module_allow_new_arb_cycle;
  wire             cpu_jtag_debug_module_any_bursting_master_saved_grant;
  wire             cpu_jtag_debug_module_any_continuerequest;
  reg     [  1: 0] cpu_jtag_debug_module_arb_addend;
  wire             cpu_jtag_debug_module_arb_counter_enable;
  reg     [  1: 0] cpu_jtag_debug_module_arb_share_counter;
  wire    [  1: 0] cpu_jtag_debug_module_arb_share_counter_next_value;
  wire    [  1: 0] cpu_jtag_debug_module_arb_share_set_values;
  wire    [  1: 0] cpu_jtag_debug_module_arb_winner;
  wire             cpu_jtag_debug_module_arbitration_holdoff_internal;
  wire             cpu_jtag_debug_module_beginbursttransfer_internal;
  wire             cpu_jtag_debug_module_begins_xfer;
  wire             cpu_jtag_debug_module_begintransfer;
  wire    [  3: 0] cpu_jtag_debug_module_byteenable;
  wire             cpu_jtag_debug_module_chipselect;
  wire    [  3: 0] cpu_jtag_debug_module_chosen_master_double_vector;
  wire    [  1: 0] cpu_jtag_debug_module_chosen_master_rot_left;
  wire             cpu_jtag_debug_module_debugaccess;
  wire             cpu_jtag_debug_module_end_xfer;
  wire             cpu_jtag_debug_module_firsttransfer;
  wire    [  1: 0] cpu_jtag_debug_module_grant_vector;
  wire             cpu_jtag_debug_module_in_a_read_cycle;
  wire             cpu_jtag_debug_module_in_a_write_cycle;
  wire    [  1: 0] cpu_jtag_debug_module_master_qreq_vector;
  wire             cpu_jtag_debug_module_non_bursting_master_requests;
  wire    [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
  reg              cpu_jtag_debug_module_reg_firsttransfer;
  wire             cpu_jtag_debug_module_reset;
  wire             cpu_jtag_debug_module_resetrequest_from_sa;
  reg     [  1: 0] cpu_jtag_debug_module_saved_chosen_master_vector;
  reg              cpu_jtag_debug_module_slavearbiterlockenable;
  wire             cpu_jtag_debug_module_slavearbiterlockenable2;
  wire             cpu_jtag_debug_module_unreg_firsttransfer;
  wire             cpu_jtag_debug_module_waits_for_read;
  wire             cpu_jtag_debug_module_waits_for_write;
  wire             cpu_jtag_debug_module_write;
  wire    [ 31: 0] cpu_jtag_debug_module_writedata;
  reg              d1_cpu_jtag_debug_module_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_cpu_jtag_debug_module;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module;
  reg              last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module;
  wire    [ 24: 0] shifted_address_to_cpu_jtag_debug_module_from_cpu_data_master;
  wire    [ 24: 0] shifted_address_to_cpu_jtag_debug_module_from_cpu_instruction_master;
  wire             wait_for_cpu_jtag_debug_module_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~cpu_jtag_debug_module_end_xfer;
    end


  assign cpu_jtag_debug_module_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_cpu_jtag_debug_module | cpu_instruction_master_qualified_request_cpu_jtag_debug_module));
  //assign cpu_jtag_debug_module_readdata_from_sa = cpu_jtag_debug_module_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cpu_jtag_debug_module_readdata_from_sa = cpu_jtag_debug_module_readdata;

  assign cpu_data_master_requests_cpu_jtag_debug_module = ({cpu_data_master_address_to_slave[24 : 11] , 11'b0} == 25'h800) & (cpu_data_master_read | cpu_data_master_write);
  //cpu_jtag_debug_module_arb_share_counter set values, which is an e_mux
  assign cpu_jtag_debug_module_arb_share_set_values = 1;

  //cpu_jtag_debug_module_non_bursting_master_requests mux, which is an e_mux
  assign cpu_jtag_debug_module_non_bursting_master_requests = cpu_data_master_requests_cpu_jtag_debug_module |
    cpu_instruction_master_requests_cpu_jtag_debug_module |
    cpu_data_master_requests_cpu_jtag_debug_module |
    cpu_instruction_master_requests_cpu_jtag_debug_module;

  //cpu_jtag_debug_module_any_bursting_master_saved_grant mux, which is an e_mux
  assign cpu_jtag_debug_module_any_bursting_master_saved_grant = 0;

  //cpu_jtag_debug_module_arb_share_counter_next_value assignment, which is an e_assign
  assign cpu_jtag_debug_module_arb_share_counter_next_value = cpu_jtag_debug_module_firsttransfer ? (cpu_jtag_debug_module_arb_share_set_values - 1) : |cpu_jtag_debug_module_arb_share_counter ? (cpu_jtag_debug_module_arb_share_counter - 1) : 0;

  //cpu_jtag_debug_module_allgrants all slave grants, which is an e_mux
  assign cpu_jtag_debug_module_allgrants = |cpu_jtag_debug_module_grant_vector |
    |cpu_jtag_debug_module_grant_vector |
    |cpu_jtag_debug_module_grant_vector |
    |cpu_jtag_debug_module_grant_vector;

  //cpu_jtag_debug_module_end_xfer assignment, which is an e_assign
  assign cpu_jtag_debug_module_end_xfer = ~(cpu_jtag_debug_module_waits_for_read | cpu_jtag_debug_module_waits_for_write);

  //end_xfer_arb_share_counter_term_cpu_jtag_debug_module arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_cpu_jtag_debug_module = cpu_jtag_debug_module_end_xfer & (~cpu_jtag_debug_module_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //cpu_jtag_debug_module_arb_share_counter arbitration counter enable, which is an e_assign
  assign cpu_jtag_debug_module_arb_counter_enable = (end_xfer_arb_share_counter_term_cpu_jtag_debug_module & cpu_jtag_debug_module_allgrants) | (end_xfer_arb_share_counter_term_cpu_jtag_debug_module & ~cpu_jtag_debug_module_non_bursting_master_requests);

  //cpu_jtag_debug_module_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_jtag_debug_module_arb_share_counter <= 0;
      else if (cpu_jtag_debug_module_arb_counter_enable)
          cpu_jtag_debug_module_arb_share_counter <= cpu_jtag_debug_module_arb_share_counter_next_value;
    end


  //cpu_jtag_debug_module_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_jtag_debug_module_slavearbiterlockenable <= 0;
      else if ((|cpu_jtag_debug_module_master_qreq_vector & end_xfer_arb_share_counter_term_cpu_jtag_debug_module) | (end_xfer_arb_share_counter_term_cpu_jtag_debug_module & ~cpu_jtag_debug_module_non_bursting_master_requests))
          cpu_jtag_debug_module_slavearbiterlockenable <= |cpu_jtag_debug_module_arb_share_counter_next_value;
    end


  //cpu/data_master cpu/jtag_debug_module arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = cpu_jtag_debug_module_slavearbiterlockenable & cpu_data_master_continuerequest;

  //cpu_jtag_debug_module_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign cpu_jtag_debug_module_slavearbiterlockenable2 = |cpu_jtag_debug_module_arb_share_counter_next_value;

  //cpu/data_master cpu/jtag_debug_module arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = cpu_jtag_debug_module_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //cpu/instruction_master cpu/jtag_debug_module arbiterlock, which is an e_assign
  assign cpu_instruction_master_arbiterlock = cpu_jtag_debug_module_slavearbiterlockenable & cpu_instruction_master_continuerequest;

  //cpu/instruction_master cpu/jtag_debug_module arbiterlock2, which is an e_assign
  assign cpu_instruction_master_arbiterlock2 = cpu_jtag_debug_module_slavearbiterlockenable2 & cpu_instruction_master_continuerequest;

  //cpu/instruction_master granted cpu/jtag_debug_module last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module <= 0;
      else if (1)
          last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module <= cpu_instruction_master_saved_grant_cpu_jtag_debug_module ? 1 : (cpu_jtag_debug_module_arbitration_holdoff_internal | ~cpu_instruction_master_requests_cpu_jtag_debug_module) ? 0 : last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module;
    end


  //cpu_instruction_master_continuerequest continued request, which is an e_mux
  assign cpu_instruction_master_continuerequest = last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module & cpu_instruction_master_requests_cpu_jtag_debug_module;

  //cpu_jtag_debug_module_any_continuerequest at least one master continues requesting, which is an e_mux
  assign cpu_jtag_debug_module_any_continuerequest = cpu_instruction_master_continuerequest |
    cpu_data_master_continuerequest;

  assign cpu_data_master_qualified_request_cpu_jtag_debug_module = cpu_data_master_requests_cpu_jtag_debug_module & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write) | cpu_instruction_master_arbiterlock);
  //cpu_jtag_debug_module_writedata mux, which is an e_mux
  assign cpu_jtag_debug_module_writedata = cpu_data_master_writedata;

  assign cpu_instruction_master_requests_cpu_jtag_debug_module = (({cpu_instruction_master_address_to_slave[24 : 11] , 11'b0} == 25'h800) & (cpu_instruction_master_read)) & cpu_instruction_master_read;
  //cpu/data_master granted cpu/jtag_debug_module last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module <= 0;
      else if (1)
          last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module <= cpu_data_master_saved_grant_cpu_jtag_debug_module ? 1 : (cpu_jtag_debug_module_arbitration_holdoff_internal | ~cpu_data_master_requests_cpu_jtag_debug_module) ? 0 : last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module;
    end


  //cpu_data_master_continuerequest continued request, which is an e_mux
  assign cpu_data_master_continuerequest = last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module & cpu_data_master_requests_cpu_jtag_debug_module;

  assign cpu_instruction_master_qualified_request_cpu_jtag_debug_module = cpu_instruction_master_requests_cpu_jtag_debug_module & ~((cpu_instruction_master_read & ((cpu_instruction_master_latency_counter != 0))) | cpu_data_master_arbiterlock);
  //local readdatavalid cpu_instruction_master_read_data_valid_cpu_jtag_debug_module, which is an e_mux
  assign cpu_instruction_master_read_data_valid_cpu_jtag_debug_module = cpu_instruction_master_granted_cpu_jtag_debug_module & cpu_instruction_master_read & ~cpu_jtag_debug_module_waits_for_read;

  //allow new arb cycle for cpu/jtag_debug_module, which is an e_assign
  assign cpu_jtag_debug_module_allow_new_arb_cycle = ~cpu_data_master_arbiterlock & ~cpu_instruction_master_arbiterlock;

  //cpu/instruction_master assignment into master qualified-requests vector for cpu/jtag_debug_module, which is an e_assign
  assign cpu_jtag_debug_module_master_qreq_vector[0] = cpu_instruction_master_qualified_request_cpu_jtag_debug_module;

  //cpu/instruction_master grant cpu/jtag_debug_module, which is an e_assign
  assign cpu_instruction_master_granted_cpu_jtag_debug_module = cpu_jtag_debug_module_grant_vector[0];

  //cpu/instruction_master saved-grant cpu/jtag_debug_module, which is an e_assign
  assign cpu_instruction_master_saved_grant_cpu_jtag_debug_module = cpu_jtag_debug_module_arb_winner[0] && cpu_instruction_master_requests_cpu_jtag_debug_module;

  //cpu/data_master assignment into master qualified-requests vector for cpu/jtag_debug_module, which is an e_assign
  assign cpu_jtag_debug_module_master_qreq_vector[1] = cpu_data_master_qualified_request_cpu_jtag_debug_module;

  //cpu/data_master grant cpu/jtag_debug_module, which is an e_assign
  assign cpu_data_master_granted_cpu_jtag_debug_module = cpu_jtag_debug_module_grant_vector[1];

  //cpu/data_master saved-grant cpu/jtag_debug_module, which is an e_assign
  assign cpu_data_master_saved_grant_cpu_jtag_debug_module = cpu_jtag_debug_module_arb_winner[1] && cpu_data_master_requests_cpu_jtag_debug_module;

  //cpu/jtag_debug_module chosen-master double-vector, which is an e_assign
  assign cpu_jtag_debug_module_chosen_master_double_vector = {cpu_jtag_debug_module_master_qreq_vector, cpu_jtag_debug_module_master_qreq_vector} & ({~cpu_jtag_debug_module_master_qreq_vector, ~cpu_jtag_debug_module_master_qreq_vector} + cpu_jtag_debug_module_arb_addend);

  //stable onehot encoding of arb winner
  assign cpu_jtag_debug_module_arb_winner = (cpu_jtag_debug_module_allow_new_arb_cycle & | cpu_jtag_debug_module_grant_vector) ? cpu_jtag_debug_module_grant_vector : cpu_jtag_debug_module_saved_chosen_master_vector;

  //saved cpu_jtag_debug_module_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_jtag_debug_module_saved_chosen_master_vector <= 0;
      else if (cpu_jtag_debug_module_allow_new_arb_cycle)
          cpu_jtag_debug_module_saved_chosen_master_vector <= |cpu_jtag_debug_module_grant_vector ? cpu_jtag_debug_module_grant_vector : cpu_jtag_debug_module_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign cpu_jtag_debug_module_grant_vector = {(cpu_jtag_debug_module_chosen_master_double_vector[1] | cpu_jtag_debug_module_chosen_master_double_vector[3]),
    (cpu_jtag_debug_module_chosen_master_double_vector[0] | cpu_jtag_debug_module_chosen_master_double_vector[2])};

  //cpu/jtag_debug_module chosen master rotated left, which is an e_assign
  assign cpu_jtag_debug_module_chosen_master_rot_left = (cpu_jtag_debug_module_arb_winner << 1) ? (cpu_jtag_debug_module_arb_winner << 1) : 1;

  //cpu/jtag_debug_module's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_jtag_debug_module_arb_addend <= 1;
      else if (|cpu_jtag_debug_module_grant_vector)
          cpu_jtag_debug_module_arb_addend <= cpu_jtag_debug_module_end_xfer? cpu_jtag_debug_module_chosen_master_rot_left : cpu_jtag_debug_module_grant_vector;
    end


  assign cpu_jtag_debug_module_begintransfer = cpu_jtag_debug_module_begins_xfer;
  //~cpu_jtag_debug_module_reset assignment, which is an e_assign
  assign cpu_jtag_debug_module_reset = ~reset_n;

  //assign cpu_jtag_debug_module_resetrequest_from_sa = cpu_jtag_debug_module_resetrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cpu_jtag_debug_module_resetrequest_from_sa = cpu_jtag_debug_module_resetrequest;

  assign cpu_jtag_debug_module_chipselect = cpu_data_master_granted_cpu_jtag_debug_module | cpu_instruction_master_granted_cpu_jtag_debug_module;
  //cpu_jtag_debug_module_firsttransfer first transaction, which is an e_assign
  assign cpu_jtag_debug_module_firsttransfer = cpu_jtag_debug_module_begins_xfer ? cpu_jtag_debug_module_unreg_firsttransfer : cpu_jtag_debug_module_reg_firsttransfer;

  //cpu_jtag_debug_module_unreg_firsttransfer first transaction, which is an e_assign
  assign cpu_jtag_debug_module_unreg_firsttransfer = ~(cpu_jtag_debug_module_slavearbiterlockenable & cpu_jtag_debug_module_any_continuerequest);

  //cpu_jtag_debug_module_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_jtag_debug_module_reg_firsttransfer <= 1'b1;
      else if (cpu_jtag_debug_module_begins_xfer)
          cpu_jtag_debug_module_reg_firsttransfer <= cpu_jtag_debug_module_unreg_firsttransfer;
    end


  //cpu_jtag_debug_module_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign cpu_jtag_debug_module_beginbursttransfer_internal = cpu_jtag_debug_module_begins_xfer;

  //cpu_jtag_debug_module_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign cpu_jtag_debug_module_arbitration_holdoff_internal = cpu_jtag_debug_module_begins_xfer & cpu_jtag_debug_module_firsttransfer;

  //cpu_jtag_debug_module_write assignment, which is an e_mux
  assign cpu_jtag_debug_module_write = cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_write;

  assign shifted_address_to_cpu_jtag_debug_module_from_cpu_data_master = cpu_data_master_address_to_slave;
  //cpu_jtag_debug_module_address mux, which is an e_mux
  assign cpu_jtag_debug_module_address = (cpu_data_master_granted_cpu_jtag_debug_module)? (shifted_address_to_cpu_jtag_debug_module_from_cpu_data_master >> 2) :
    (shifted_address_to_cpu_jtag_debug_module_from_cpu_instruction_master >> 2);

  assign shifted_address_to_cpu_jtag_debug_module_from_cpu_instruction_master = cpu_instruction_master_address_to_slave;
  //d1_cpu_jtag_debug_module_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_cpu_jtag_debug_module_end_xfer <= 1;
      else if (1)
          d1_cpu_jtag_debug_module_end_xfer <= cpu_jtag_debug_module_end_xfer;
    end


  //cpu_jtag_debug_module_waits_for_read in a cycle, which is an e_mux
  assign cpu_jtag_debug_module_waits_for_read = cpu_jtag_debug_module_in_a_read_cycle & cpu_jtag_debug_module_begins_xfer;

  //cpu_jtag_debug_module_in_a_read_cycle assignment, which is an e_assign
  assign cpu_jtag_debug_module_in_a_read_cycle = (cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_read) | (cpu_instruction_master_granted_cpu_jtag_debug_module & cpu_instruction_master_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = cpu_jtag_debug_module_in_a_read_cycle;

  //cpu_jtag_debug_module_waits_for_write in a cycle, which is an e_mux
  assign cpu_jtag_debug_module_waits_for_write = cpu_jtag_debug_module_in_a_write_cycle & 0;

  //cpu_jtag_debug_module_in_a_write_cycle assignment, which is an e_assign
  assign cpu_jtag_debug_module_in_a_write_cycle = cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = cpu_jtag_debug_module_in_a_write_cycle;

  assign wait_for_cpu_jtag_debug_module_counter = 0;
  //cpu_jtag_debug_module_byteenable byte enable port mux, which is an e_mux
  assign cpu_jtag_debug_module_byteenable = (cpu_data_master_granted_cpu_jtag_debug_module)? cpu_data_master_byteenable :
    -1;

  //debugaccess mux, which is an e_mux
  assign cpu_jtag_debug_module_debugaccess = (cpu_data_master_granted_cpu_jtag_debug_module)? cpu_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //cpu/jtag_debug_module enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end


  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_granted_cpu_jtag_debug_module + cpu_instruction_master_granted_cpu_jtag_debug_module > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_saved_grant_cpu_jtag_debug_module + cpu_instruction_master_saved_grant_cpu_jtag_debug_module > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_custom_instruction_master_arbitrator (
                                                  // inputs:
                                                   clk,
                                                   cpu_custom_instruction_master_multi_start,
                                                   cpu_fpoint_s1_done_from_sa,
                                                   cpu_fpoint_s1_result_from_sa,
                                                   reset_n,

                                                  // outputs:
                                                   cpu_custom_instruction_master_multi_done,
                                                   cpu_custom_instruction_master_multi_result,
                                                   cpu_custom_instruction_master_reset_n,
                                                   cpu_custom_instruction_master_start_cpu_fpoint_s1,
                                                   cpu_fpoint_s1_select
                                                )
;

  output           cpu_custom_instruction_master_multi_done;
  output  [ 31: 0] cpu_custom_instruction_master_multi_result;
  output           cpu_custom_instruction_master_reset_n;
  output           cpu_custom_instruction_master_start_cpu_fpoint_s1;
  output           cpu_fpoint_s1_select;
  input            clk;
  input            cpu_custom_instruction_master_multi_start;
  input            cpu_fpoint_s1_done_from_sa;
  input   [ 31: 0] cpu_fpoint_s1_result_from_sa;
  input            reset_n;

  wire             cpu_custom_instruction_master_multi_done;
  wire    [ 31: 0] cpu_custom_instruction_master_multi_result;
  wire             cpu_custom_instruction_master_reset_n;
  wire             cpu_custom_instruction_master_start_cpu_fpoint_s1;
  wire             cpu_fpoint_s1_select;
  assign cpu_fpoint_s1_select = 1'b1;
  assign cpu_custom_instruction_master_start_cpu_fpoint_s1 = cpu_fpoint_s1_select & cpu_custom_instruction_master_multi_start;
  //cpu_custom_instruction_master_multi_result mux, which is an e_mux
  assign cpu_custom_instruction_master_multi_result = {32 {cpu_fpoint_s1_select}} & cpu_fpoint_s1_result_from_sa;

  //multi_done mux, which is an e_mux
  assign cpu_custom_instruction_master_multi_done = {1 {cpu_fpoint_s1_select}} & cpu_fpoint_s1_done_from_sa;

  //cpu_custom_instruction_master_reset_n local reset_n, which is an e_assign
  assign cpu_custom_instruction_master_reset_n = reset_n;


endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_data_master_arbitrator (
                                    // inputs:
                                     AREA_s1_readdata_from_sa,
                                     RESET_s1_readdata_from_sa,
                                     XOFF_s1_readdata_from_sa,
                                     YOFF_s1_readdata_from_sa,
                                     clk,
                                     cpu_data_master_address,
                                     cpu_data_master_byteenable_onchip_mem_s1,
                                     cpu_data_master_granted_AREA_s1,
                                     cpu_data_master_granted_B1_s1,
                                     cpu_data_master_granted_B2_s1,
                                     cpu_data_master_granted_B3_s1,
                                     cpu_data_master_granted_B4_s1,
                                     cpu_data_master_granted_B5_s1,
                                     cpu_data_master_granted_B6_s1,
                                     cpu_data_master_granted_B7_s1,
                                     cpu_data_master_granted_B8_s1,
                                     cpu_data_master_granted_RESET_s1,
                                     cpu_data_master_granted_XOFF_s1,
                                     cpu_data_master_granted_YOFF_s1,
                                     cpu_data_master_granted_cpu_jtag_debug_module,
                                     cpu_data_master_granted_goIN_s1,
                                     cpu_data_master_granted_goOUT_s1,
                                     cpu_data_master_granted_jtag_uart_avalon_jtag_slave,
                                     cpu_data_master_granted_onchip_mem_s1,
                                     cpu_data_master_qualified_request_AREA_s1,
                                     cpu_data_master_qualified_request_B1_s1,
                                     cpu_data_master_qualified_request_B2_s1,
                                     cpu_data_master_qualified_request_B3_s1,
                                     cpu_data_master_qualified_request_B4_s1,
                                     cpu_data_master_qualified_request_B5_s1,
                                     cpu_data_master_qualified_request_B6_s1,
                                     cpu_data_master_qualified_request_B7_s1,
                                     cpu_data_master_qualified_request_B8_s1,
                                     cpu_data_master_qualified_request_RESET_s1,
                                     cpu_data_master_qualified_request_XOFF_s1,
                                     cpu_data_master_qualified_request_YOFF_s1,
                                     cpu_data_master_qualified_request_cpu_jtag_debug_module,
                                     cpu_data_master_qualified_request_goIN_s1,
                                     cpu_data_master_qualified_request_goOUT_s1,
                                     cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave,
                                     cpu_data_master_qualified_request_onchip_mem_s1,
                                     cpu_data_master_read,
                                     cpu_data_master_read_data_valid_AREA_s1,
                                     cpu_data_master_read_data_valid_B1_s1,
                                     cpu_data_master_read_data_valid_B2_s1,
                                     cpu_data_master_read_data_valid_B3_s1,
                                     cpu_data_master_read_data_valid_B4_s1,
                                     cpu_data_master_read_data_valid_B5_s1,
                                     cpu_data_master_read_data_valid_B6_s1,
                                     cpu_data_master_read_data_valid_B7_s1,
                                     cpu_data_master_read_data_valid_B8_s1,
                                     cpu_data_master_read_data_valid_RESET_s1,
                                     cpu_data_master_read_data_valid_XOFF_s1,
                                     cpu_data_master_read_data_valid_YOFF_s1,
                                     cpu_data_master_read_data_valid_cpu_jtag_debug_module,
                                     cpu_data_master_read_data_valid_goIN_s1,
                                     cpu_data_master_read_data_valid_goOUT_s1,
                                     cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave,
                                     cpu_data_master_read_data_valid_onchip_mem_s1,
                                     cpu_data_master_requests_AREA_s1,
                                     cpu_data_master_requests_B1_s1,
                                     cpu_data_master_requests_B2_s1,
                                     cpu_data_master_requests_B3_s1,
                                     cpu_data_master_requests_B4_s1,
                                     cpu_data_master_requests_B5_s1,
                                     cpu_data_master_requests_B6_s1,
                                     cpu_data_master_requests_B7_s1,
                                     cpu_data_master_requests_B8_s1,
                                     cpu_data_master_requests_RESET_s1,
                                     cpu_data_master_requests_XOFF_s1,
                                     cpu_data_master_requests_YOFF_s1,
                                     cpu_data_master_requests_cpu_jtag_debug_module,
                                     cpu_data_master_requests_goIN_s1,
                                     cpu_data_master_requests_goOUT_s1,
                                     cpu_data_master_requests_jtag_uart_avalon_jtag_slave,
                                     cpu_data_master_requests_onchip_mem_s1,
                                     cpu_data_master_write,
                                     cpu_data_master_writedata,
                                     cpu_jtag_debug_module_readdata_from_sa,
                                     d1_AREA_s1_end_xfer,
                                     d1_B1_s1_end_xfer,
                                     d1_B2_s1_end_xfer,
                                     d1_B3_s1_end_xfer,
                                     d1_B4_s1_end_xfer,
                                     d1_B5_s1_end_xfer,
                                     d1_B6_s1_end_xfer,
                                     d1_B7_s1_end_xfer,
                                     d1_B8_s1_end_xfer,
                                     d1_RESET_s1_end_xfer,
                                     d1_XOFF_s1_end_xfer,
                                     d1_YOFF_s1_end_xfer,
                                     d1_cpu_jtag_debug_module_end_xfer,
                                     d1_goIN_s1_end_xfer,
                                     d1_goOUT_s1_end_xfer,
                                     d1_jtag_uart_avalon_jtag_slave_end_xfer,
                                     d1_onchip_mem_s1_end_xfer,
                                     goIN_s1_readdata_from_sa,
                                     jtag_uart_avalon_jtag_slave_irq_from_sa,
                                     jtag_uart_avalon_jtag_slave_readdata_from_sa,
                                     jtag_uart_avalon_jtag_slave_waitrequest_from_sa,
                                     onchip_mem_s1_readdata_from_sa,
                                     registered_cpu_data_master_read_data_valid_onchip_mem_s1,
                                     reset_n,

                                    // outputs:
                                     cpu_data_master_address_to_slave,
                                     cpu_data_master_dbs_address,
                                     cpu_data_master_dbs_write_16,
                                     cpu_data_master_irq,
                                     cpu_data_master_no_byte_enables_and_last_term,
                                     cpu_data_master_readdata,
                                     cpu_data_master_waitrequest
                                  )
;

  output  [ 24: 0] cpu_data_master_address_to_slave;
  output  [  1: 0] cpu_data_master_dbs_address;
  output  [ 15: 0] cpu_data_master_dbs_write_16;
  output  [ 31: 0] cpu_data_master_irq;
  output           cpu_data_master_no_byte_enables_and_last_term;
  output  [ 31: 0] cpu_data_master_readdata;
  output           cpu_data_master_waitrequest;
  input   [ 31: 0] AREA_s1_readdata_from_sa;
  input            RESET_s1_readdata_from_sa;
  input   [  8: 0] XOFF_s1_readdata_from_sa;
  input   [  8: 0] YOFF_s1_readdata_from_sa;
  input            clk;
  input   [ 24: 0] cpu_data_master_address;
  input   [  1: 0] cpu_data_master_byteenable_onchip_mem_s1;
  input            cpu_data_master_granted_AREA_s1;
  input            cpu_data_master_granted_B1_s1;
  input            cpu_data_master_granted_B2_s1;
  input            cpu_data_master_granted_B3_s1;
  input            cpu_data_master_granted_B4_s1;
  input            cpu_data_master_granted_B5_s1;
  input            cpu_data_master_granted_B6_s1;
  input            cpu_data_master_granted_B7_s1;
  input            cpu_data_master_granted_B8_s1;
  input            cpu_data_master_granted_RESET_s1;
  input            cpu_data_master_granted_XOFF_s1;
  input            cpu_data_master_granted_YOFF_s1;
  input            cpu_data_master_granted_cpu_jtag_debug_module;
  input            cpu_data_master_granted_goIN_s1;
  input            cpu_data_master_granted_goOUT_s1;
  input            cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
  input            cpu_data_master_granted_onchip_mem_s1;
  input            cpu_data_master_qualified_request_AREA_s1;
  input            cpu_data_master_qualified_request_B1_s1;
  input            cpu_data_master_qualified_request_B2_s1;
  input            cpu_data_master_qualified_request_B3_s1;
  input            cpu_data_master_qualified_request_B4_s1;
  input            cpu_data_master_qualified_request_B5_s1;
  input            cpu_data_master_qualified_request_B6_s1;
  input            cpu_data_master_qualified_request_B7_s1;
  input            cpu_data_master_qualified_request_B8_s1;
  input            cpu_data_master_qualified_request_RESET_s1;
  input            cpu_data_master_qualified_request_XOFF_s1;
  input            cpu_data_master_qualified_request_YOFF_s1;
  input            cpu_data_master_qualified_request_cpu_jtag_debug_module;
  input            cpu_data_master_qualified_request_goIN_s1;
  input            cpu_data_master_qualified_request_goOUT_s1;
  input            cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
  input            cpu_data_master_qualified_request_onchip_mem_s1;
  input            cpu_data_master_read;
  input            cpu_data_master_read_data_valid_AREA_s1;
  input            cpu_data_master_read_data_valid_B1_s1;
  input            cpu_data_master_read_data_valid_B2_s1;
  input            cpu_data_master_read_data_valid_B3_s1;
  input            cpu_data_master_read_data_valid_B4_s1;
  input            cpu_data_master_read_data_valid_B5_s1;
  input            cpu_data_master_read_data_valid_B6_s1;
  input            cpu_data_master_read_data_valid_B7_s1;
  input            cpu_data_master_read_data_valid_B8_s1;
  input            cpu_data_master_read_data_valid_RESET_s1;
  input            cpu_data_master_read_data_valid_XOFF_s1;
  input            cpu_data_master_read_data_valid_YOFF_s1;
  input            cpu_data_master_read_data_valid_cpu_jtag_debug_module;
  input            cpu_data_master_read_data_valid_goIN_s1;
  input            cpu_data_master_read_data_valid_goOUT_s1;
  input            cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
  input            cpu_data_master_read_data_valid_onchip_mem_s1;
  input            cpu_data_master_requests_AREA_s1;
  input            cpu_data_master_requests_B1_s1;
  input            cpu_data_master_requests_B2_s1;
  input            cpu_data_master_requests_B3_s1;
  input            cpu_data_master_requests_B4_s1;
  input            cpu_data_master_requests_B5_s1;
  input            cpu_data_master_requests_B6_s1;
  input            cpu_data_master_requests_B7_s1;
  input            cpu_data_master_requests_B8_s1;
  input            cpu_data_master_requests_RESET_s1;
  input            cpu_data_master_requests_XOFF_s1;
  input            cpu_data_master_requests_YOFF_s1;
  input            cpu_data_master_requests_cpu_jtag_debug_module;
  input            cpu_data_master_requests_goIN_s1;
  input            cpu_data_master_requests_goOUT_s1;
  input            cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
  input            cpu_data_master_requests_onchip_mem_s1;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input   [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
  input            d1_AREA_s1_end_xfer;
  input            d1_B1_s1_end_xfer;
  input            d1_B2_s1_end_xfer;
  input            d1_B3_s1_end_xfer;
  input            d1_B4_s1_end_xfer;
  input            d1_B5_s1_end_xfer;
  input            d1_B6_s1_end_xfer;
  input            d1_B7_s1_end_xfer;
  input            d1_B8_s1_end_xfer;
  input            d1_RESET_s1_end_xfer;
  input            d1_XOFF_s1_end_xfer;
  input            d1_YOFF_s1_end_xfer;
  input            d1_cpu_jtag_debug_module_end_xfer;
  input            d1_goIN_s1_end_xfer;
  input            d1_goOUT_s1_end_xfer;
  input            d1_jtag_uart_avalon_jtag_slave_end_xfer;
  input            d1_onchip_mem_s1_end_xfer;
  input            goIN_s1_readdata_from_sa;
  input            jtag_uart_avalon_jtag_slave_irq_from_sa;
  input   [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
  input            jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
  input   [ 15: 0] onchip_mem_s1_readdata_from_sa;
  input            registered_cpu_data_master_read_data_valid_onchip_mem_s1;
  input            reset_n;

  wire    [ 24: 0] cpu_data_master_address_to_slave;
  reg     [  1: 0] cpu_data_master_dbs_address;
  wire    [  1: 0] cpu_data_master_dbs_increment;
  wire    [ 15: 0] cpu_data_master_dbs_write_16;
  wire    [ 31: 0] cpu_data_master_irq;
  reg              cpu_data_master_no_byte_enables_and_last_term;
  wire    [ 31: 0] cpu_data_master_readdata;
  wire             cpu_data_master_run;
  reg              cpu_data_master_waitrequest;
  reg     [ 15: 0] dbs_16_reg_segment_0;
  wire             dbs_count_enable;
  wire             dbs_counter_overflow;
  wire             last_dbs_term_and_run;
  wire    [  1: 0] next_dbs_address;
  wire    [ 15: 0] p1_dbs_16_reg_segment_0;
  wire    [ 31: 0] p1_registered_cpu_data_master_readdata;
  wire             pre_dbs_count_enable;
  wire             r_0;
  wire             r_1;
  wire             r_2;
  wire             r_3;
  reg     [ 31: 0] registered_cpu_data_master_readdata;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & ((~cpu_data_master_qualified_request_AREA_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_AREA_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_B1_s1 | ~cpu_data_master_requests_B1_s1) & ((~cpu_data_master_qualified_request_B1_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_B1_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_B2_s1 | ~cpu_data_master_requests_B2_s1) & ((~cpu_data_master_qualified_request_B2_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_B2_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_B3_s1 | ~cpu_data_master_requests_B3_s1) & ((~cpu_data_master_qualified_request_B3_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_B3_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_B4_s1 | ~cpu_data_master_requests_B4_s1) & ((~cpu_data_master_qualified_request_B4_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_B4_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1;

  //cascaded wait assignment, which is an e_assign
  assign cpu_data_master_run = r_0 & r_1 & r_2 & r_3;

  //r_1 master_run cascaded wait assignment, which is an e_assign
  assign r_1 = (cpu_data_master_qualified_request_B5_s1 | ~cpu_data_master_requests_B5_s1) & ((~cpu_data_master_qualified_request_B5_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_B5_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_B6_s1 | ~cpu_data_master_requests_B6_s1) & ((~cpu_data_master_qualified_request_B6_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_B6_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_B7_s1 | ~cpu_data_master_requests_B7_s1) & ((~cpu_data_master_qualified_request_B7_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_B7_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_B8_s1 | ~cpu_data_master_requests_B8_s1) & ((~cpu_data_master_qualified_request_B8_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_B8_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & ((~cpu_data_master_qualified_request_RESET_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_RESET_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & ((~cpu_data_master_qualified_request_XOFF_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read)));

  //r_2 master_run cascaded wait assignment, which is an e_assign
  assign r_2 = ((~cpu_data_master_qualified_request_XOFF_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & ((~cpu_data_master_qualified_request_YOFF_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_YOFF_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_cpu_jtag_debug_module | ~cpu_data_master_requests_cpu_jtag_debug_module) & (cpu_data_master_granted_cpu_jtag_debug_module | ~cpu_data_master_qualified_request_cpu_jtag_debug_module) & ((~cpu_data_master_qualified_request_cpu_jtag_debug_module | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_cpu_jtag_debug_module | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & ((~cpu_data_master_qualified_request_goIN_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_goIN_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_goOUT_s1 | ~cpu_data_master_requests_goOUT_s1) & ((~cpu_data_master_qualified_request_goOUT_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_goOUT_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~cpu_data_master_requests_jtag_uart_avalon_jtag_slave) & ((~cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~(cpu_data_master_read | cpu_data_master_write) | (1 & ~jtag_uart_avalon_jtag_slave_waitrequest_from_sa & (cpu_data_master_read | cpu_data_master_write)))) & ((~cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~(cpu_data_master_read | cpu_data_master_write) | (1 & ~jtag_uart_avalon_jtag_slave_waitrequest_from_sa & (cpu_data_master_read | cpu_data_master_write))));

  //r_3 master_run cascaded wait assignment, which is an e_assign
  assign r_3 = 1 & (cpu_data_master_qualified_request_onchip_mem_s1 | (registered_cpu_data_master_read_data_valid_onchip_mem_s1 & cpu_data_master_dbs_address[1]) | (cpu_data_master_write & !cpu_data_master_byteenable_onchip_mem_s1 & cpu_data_master_dbs_address[1]) | ~cpu_data_master_requests_onchip_mem_s1) & (cpu_data_master_granted_onchip_mem_s1 | ~cpu_data_master_qualified_request_onchip_mem_s1) & ((~cpu_data_master_qualified_request_onchip_mem_s1 | ~cpu_data_master_read | (registered_cpu_data_master_read_data_valid_onchip_mem_s1 & (cpu_data_master_dbs_address[1]) & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_onchip_mem_s1 | ~cpu_data_master_write | (1 & (cpu_data_master_dbs_address[1]) & cpu_data_master_write)));

  //optimize select-logic by passing only those address bits which matter.
  assign cpu_data_master_address_to_slave = {cpu_data_master_address[24],
    10'b0,
    cpu_data_master_address[13 : 0]};

  //cpu/data_master readdata mux, which is an e_mux
  assign cpu_data_master_readdata = ({32 {~cpu_data_master_requests_AREA_s1}} | AREA_s1_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_RESET_s1}} | RESET_s1_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_XOFF_s1}} | XOFF_s1_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_YOFF_s1}} | YOFF_s1_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_cpu_jtag_debug_module}} | cpu_jtag_debug_module_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_goIN_s1}} | goIN_s1_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_jtag_uart_avalon_jtag_slave}} | registered_cpu_data_master_readdata) &
    ({32 {~cpu_data_master_requests_onchip_mem_s1}} | {onchip_mem_s1_readdata_from_sa[15 : 0],
    dbs_16_reg_segment_0});

  //actual waitrequest port, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_waitrequest <= ~0;
      else if (1)
          cpu_data_master_waitrequest <= ~((~(cpu_data_master_read | cpu_data_master_write))? 0: (cpu_data_master_run & cpu_data_master_waitrequest));
    end


  //unpredictable registered wait state incoming data, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          registered_cpu_data_master_readdata <= 0;
      else if (1)
          registered_cpu_data_master_readdata <= p1_registered_cpu_data_master_readdata;
    end


  //registered readdata mux, which is an e_mux
  assign p1_registered_cpu_data_master_readdata = {32 {~cpu_data_master_requests_jtag_uart_avalon_jtag_slave}} | jtag_uart_avalon_jtag_slave_readdata_from_sa;

  //irq assign, which is an e_assign
  assign cpu_data_master_irq = {1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    jtag_uart_avalon_jtag_slave_irq_from_sa};

  //no_byte_enables_and_last_term, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_no_byte_enables_and_last_term <= 0;
      else if (1)
          cpu_data_master_no_byte_enables_and_last_term <= last_dbs_term_and_run;
    end


  //compute the last dbs term, which is an e_mux
  assign last_dbs_term_and_run = (cpu_data_master_dbs_address == 2'b10) & cpu_data_master_write & !cpu_data_master_byteenable_onchip_mem_s1;

  //pre dbs count enable, which is an e_mux
  assign pre_dbs_count_enable = (((~cpu_data_master_no_byte_enables_and_last_term) & cpu_data_master_requests_onchip_mem_s1 & cpu_data_master_write & !cpu_data_master_byteenable_onchip_mem_s1)) |
    cpu_data_master_read_data_valid_onchip_mem_s1 |
    (cpu_data_master_granted_onchip_mem_s1 & cpu_data_master_write & 1 & 1);

  //input to dbs-16 stored 0, which is an e_mux
  assign p1_dbs_16_reg_segment_0 = onchip_mem_s1_readdata_from_sa;

  //dbs register for dbs-16 segment 0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_16_reg_segment_0 <= 0;
      else if (dbs_count_enable & ((cpu_data_master_dbs_address[1]) == 0))
          dbs_16_reg_segment_0 <= p1_dbs_16_reg_segment_0;
    end


  //mux write dbs 1, which is an e_mux
  assign cpu_data_master_dbs_write_16 = (cpu_data_master_dbs_address[1])? cpu_data_master_writedata[31 : 16] :
    cpu_data_master_writedata[15 : 0];

  //dbs count increment, which is an e_mux
  assign cpu_data_master_dbs_increment = (cpu_data_master_requests_onchip_mem_s1)? 2 :
    0;

  //dbs counter overflow, which is an e_assign
  assign dbs_counter_overflow = cpu_data_master_dbs_address[1] & !(next_dbs_address[1]);

  //next master address, which is an e_assign
  assign next_dbs_address = cpu_data_master_dbs_address + cpu_data_master_dbs_increment;

  //dbs count enable, which is an e_mux
  assign dbs_count_enable = pre_dbs_count_enable &
    (~(cpu_data_master_requests_onchip_mem_s1 & ~cpu_data_master_waitrequest & cpu_data_master_write));

  //dbs counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_dbs_address <= 0;
      else if (dbs_count_enable)
          cpu_data_master_dbs_address <= next_dbs_address;
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_instruction_master_arbitrator (
                                           // inputs:
                                            clk,
                                            cpu_instruction_master_address,
                                            cpu_instruction_master_granted_cpu_jtag_debug_module,
                                            cpu_instruction_master_granted_onchip_mem_s1,
                                            cpu_instruction_master_qualified_request_cpu_jtag_debug_module,
                                            cpu_instruction_master_qualified_request_onchip_mem_s1,
                                            cpu_instruction_master_read,
                                            cpu_instruction_master_read_data_valid_cpu_jtag_debug_module,
                                            cpu_instruction_master_read_data_valid_onchip_mem_s1,
                                            cpu_instruction_master_requests_cpu_jtag_debug_module,
                                            cpu_instruction_master_requests_onchip_mem_s1,
                                            cpu_jtag_debug_module_readdata_from_sa,
                                            d1_cpu_jtag_debug_module_end_xfer,
                                            d1_onchip_mem_s1_end_xfer,
                                            onchip_mem_s1_readdata_from_sa,
                                            reset_n,

                                           // outputs:
                                            cpu_instruction_master_address_to_slave,
                                            cpu_instruction_master_dbs_address,
                                            cpu_instruction_master_latency_counter,
                                            cpu_instruction_master_readdata,
                                            cpu_instruction_master_readdatavalid,
                                            cpu_instruction_master_waitrequest
                                         )
;

  output  [ 24: 0] cpu_instruction_master_address_to_slave;
  output  [  1: 0] cpu_instruction_master_dbs_address;
  output           cpu_instruction_master_latency_counter;
  output  [ 31: 0] cpu_instruction_master_readdata;
  output           cpu_instruction_master_readdatavalid;
  output           cpu_instruction_master_waitrequest;
  input            clk;
  input   [ 24: 0] cpu_instruction_master_address;
  input            cpu_instruction_master_granted_cpu_jtag_debug_module;
  input            cpu_instruction_master_granted_onchip_mem_s1;
  input            cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
  input            cpu_instruction_master_qualified_request_onchip_mem_s1;
  input            cpu_instruction_master_read;
  input            cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
  input            cpu_instruction_master_read_data_valid_onchip_mem_s1;
  input            cpu_instruction_master_requests_cpu_jtag_debug_module;
  input            cpu_instruction_master_requests_onchip_mem_s1;
  input   [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
  input            d1_cpu_jtag_debug_module_end_xfer;
  input            d1_onchip_mem_s1_end_xfer;
  input   [ 15: 0] onchip_mem_s1_readdata_from_sa;
  input            reset_n;

  reg              active_and_waiting_last_time;
  reg     [ 24: 0] cpu_instruction_master_address_last_time;
  wire    [ 24: 0] cpu_instruction_master_address_to_slave;
  reg     [  1: 0] cpu_instruction_master_dbs_address;
  wire    [  1: 0] cpu_instruction_master_dbs_increment;
  reg     [  1: 0] cpu_instruction_master_dbs_rdv_counter;
  wire    [  1: 0] cpu_instruction_master_dbs_rdv_counter_inc;
  wire             cpu_instruction_master_is_granted_some_slave;
  reg              cpu_instruction_master_latency_counter;
  wire    [  1: 0] cpu_instruction_master_next_dbs_rdv_counter;
  reg              cpu_instruction_master_read_but_no_slave_selected;
  reg              cpu_instruction_master_read_last_time;
  wire    [ 31: 0] cpu_instruction_master_readdata;
  wire             cpu_instruction_master_readdatavalid;
  wire             cpu_instruction_master_run;
  wire             cpu_instruction_master_waitrequest;
  wire             dbs_count_enable;
  wire             dbs_counter_overflow;
  reg     [ 15: 0] dbs_latent_16_reg_segment_0;
  wire             dbs_rdv_count_enable;
  wire             dbs_rdv_counter_overflow;
  wire             latency_load_value;
  wire    [  1: 0] next_dbs_address;
  wire             p1_cpu_instruction_master_latency_counter;
  wire    [ 15: 0] p1_dbs_latent_16_reg_segment_0;
  wire             pre_dbs_count_enable;
  wire             pre_flush_cpu_instruction_master_readdatavalid;
  wire             r_2;
  wire             r_3;
  //r_2 master_run cascaded wait assignment, which is an e_assign
  assign r_2 = 1 & (cpu_instruction_master_qualified_request_cpu_jtag_debug_module | ~cpu_instruction_master_requests_cpu_jtag_debug_module) & (cpu_instruction_master_granted_cpu_jtag_debug_module | ~cpu_instruction_master_qualified_request_cpu_jtag_debug_module) & ((~cpu_instruction_master_qualified_request_cpu_jtag_debug_module | ~cpu_instruction_master_read | (1 & ~d1_cpu_jtag_debug_module_end_xfer & cpu_instruction_master_read)));

  //cascaded wait assignment, which is an e_assign
  assign cpu_instruction_master_run = r_2 & r_3;

  //r_3 master_run cascaded wait assignment, which is an e_assign
  assign r_3 = 1 & (cpu_instruction_master_qualified_request_onchip_mem_s1 | ~cpu_instruction_master_requests_onchip_mem_s1) & (cpu_instruction_master_granted_onchip_mem_s1 | ~cpu_instruction_master_qualified_request_onchip_mem_s1) & ((~cpu_instruction_master_qualified_request_onchip_mem_s1 | ~cpu_instruction_master_read | (1 & (cpu_instruction_master_dbs_address[1]) & cpu_instruction_master_read)));

  //optimize select-logic by passing only those address bits which matter.
  assign cpu_instruction_master_address_to_slave = {cpu_instruction_master_address[24],
    10'b0,
    cpu_instruction_master_address[13 : 0]};

  //cpu_instruction_master_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_read_but_no_slave_selected <= 0;
      else if (1)
          cpu_instruction_master_read_but_no_slave_selected <= cpu_instruction_master_read & cpu_instruction_master_run & ~cpu_instruction_master_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign cpu_instruction_master_is_granted_some_slave = cpu_instruction_master_granted_cpu_jtag_debug_module |
    cpu_instruction_master_granted_onchip_mem_s1;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_cpu_instruction_master_readdatavalid = cpu_instruction_master_read_data_valid_onchip_mem_s1 & dbs_rdv_counter_overflow;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign cpu_instruction_master_readdatavalid = cpu_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_instruction_master_readdatavalid |
    cpu_instruction_master_read_data_valid_cpu_jtag_debug_module |
    cpu_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_instruction_master_readdatavalid;

  //cpu/instruction_master readdata mux, which is an e_mux
  assign cpu_instruction_master_readdata = ({32 {~(cpu_instruction_master_qualified_request_cpu_jtag_debug_module & cpu_instruction_master_read)}} | cpu_jtag_debug_module_readdata_from_sa) &
    ({32 {~cpu_instruction_master_read_data_valid_onchip_mem_s1}} | {onchip_mem_s1_readdata_from_sa[15 : 0],
    dbs_latent_16_reg_segment_0});

  //actual waitrequest port, which is an e_assign
  assign cpu_instruction_master_waitrequest = ~cpu_instruction_master_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_latency_counter <= 0;
      else if (1)
          cpu_instruction_master_latency_counter <= p1_cpu_instruction_master_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_cpu_instruction_master_latency_counter = ((cpu_instruction_master_run & cpu_instruction_master_read))? latency_load_value :
    (cpu_instruction_master_latency_counter)? cpu_instruction_master_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = {1 {cpu_instruction_master_requests_onchip_mem_s1}} & 1;

  //input to latent dbs-16 stored 0, which is an e_mux
  assign p1_dbs_latent_16_reg_segment_0 = onchip_mem_s1_readdata_from_sa;

  //dbs register for latent dbs-16 segment 0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_latent_16_reg_segment_0 <= 0;
      else if (dbs_rdv_count_enable & ((cpu_instruction_master_dbs_rdv_counter[1]) == 0))
          dbs_latent_16_reg_segment_0 <= p1_dbs_latent_16_reg_segment_0;
    end


  //dbs count increment, which is an e_mux
  assign cpu_instruction_master_dbs_increment = (cpu_instruction_master_requests_onchip_mem_s1)? 2 :
    0;

  //dbs counter overflow, which is an e_assign
  assign dbs_counter_overflow = cpu_instruction_master_dbs_address[1] & !(next_dbs_address[1]);

  //next master address, which is an e_assign
  assign next_dbs_address = cpu_instruction_master_dbs_address + cpu_instruction_master_dbs_increment;

  //dbs count enable, which is an e_mux
  assign dbs_count_enable = pre_dbs_count_enable;

  //dbs counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_dbs_address <= 0;
      else if (dbs_count_enable)
          cpu_instruction_master_dbs_address <= next_dbs_address;
    end


  //p1 dbs rdv counter, which is an e_assign
  assign cpu_instruction_master_next_dbs_rdv_counter = cpu_instruction_master_dbs_rdv_counter + cpu_instruction_master_dbs_rdv_counter_inc;

  //cpu_instruction_master_rdv_inc_mux, which is an e_mux
  assign cpu_instruction_master_dbs_rdv_counter_inc = 2;

  //master any slave rdv, which is an e_mux
  assign dbs_rdv_count_enable = cpu_instruction_master_read_data_valid_onchip_mem_s1;

  //dbs rdv counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_dbs_rdv_counter <= 0;
      else if (dbs_rdv_count_enable)
          cpu_instruction_master_dbs_rdv_counter <= cpu_instruction_master_next_dbs_rdv_counter;
    end


  //dbs rdv counter overflow, which is an e_assign
  assign dbs_rdv_counter_overflow = cpu_instruction_master_dbs_rdv_counter[1] & ~cpu_instruction_master_next_dbs_rdv_counter[1];

  //pre dbs count enable, which is an e_mux
  assign pre_dbs_count_enable = cpu_instruction_master_granted_onchip_mem_s1 & cpu_instruction_master_read & 1 & 1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //cpu_instruction_master_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_address_last_time <= 0;
      else if (1)
          cpu_instruction_master_address_last_time <= cpu_instruction_master_address;
    end


  //cpu/instruction_master waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else if (1)
          active_and_waiting_last_time <= cpu_instruction_master_waitrequest & (cpu_instruction_master_read);
    end


  //cpu_instruction_master_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_instruction_master_address != cpu_instruction_master_address_last_time))
        begin
          $write("%0d ns: cpu_instruction_master_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //cpu_instruction_master_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_read_last_time <= 0;
      else if (1)
          cpu_instruction_master_read_last_time <= cpu_instruction_master_read;
    end


  //cpu_instruction_master_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_instruction_master_read != cpu_instruction_master_read_last_time))
        begin
          $write("%0d ns: cpu_instruction_master_read did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_fpoint_s1_arbitrator (
                                  // inputs:
                                   clk,
                                   cpu_custom_instruction_master_multi_clk_en,
                                   cpu_custom_instruction_master_multi_dataa,
                                   cpu_custom_instruction_master_multi_datab,
                                   cpu_custom_instruction_master_multi_n,
                                   cpu_custom_instruction_master_start_cpu_fpoint_s1,
                                   cpu_fpoint_s1_done,
                                   cpu_fpoint_s1_result,
                                   cpu_fpoint_s1_select,
                                   reset_n,

                                  // outputs:
                                   cpu_fpoint_s1_clk_en,
                                   cpu_fpoint_s1_dataa,
                                   cpu_fpoint_s1_datab,
                                   cpu_fpoint_s1_done_from_sa,
                                   cpu_fpoint_s1_n,
                                   cpu_fpoint_s1_reset,
                                   cpu_fpoint_s1_result_from_sa,
                                   cpu_fpoint_s1_start
                                )
;

  output           cpu_fpoint_s1_clk_en;
  output  [ 31: 0] cpu_fpoint_s1_dataa;
  output  [ 31: 0] cpu_fpoint_s1_datab;
  output           cpu_fpoint_s1_done_from_sa;
  output  [  1: 0] cpu_fpoint_s1_n;
  output           cpu_fpoint_s1_reset;
  output  [ 31: 0] cpu_fpoint_s1_result_from_sa;
  output           cpu_fpoint_s1_start;
  input            clk;
  input            cpu_custom_instruction_master_multi_clk_en;
  input   [ 31: 0] cpu_custom_instruction_master_multi_dataa;
  input   [ 31: 0] cpu_custom_instruction_master_multi_datab;
  input   [  7: 0] cpu_custom_instruction_master_multi_n;
  input            cpu_custom_instruction_master_start_cpu_fpoint_s1;
  input            cpu_fpoint_s1_done;
  input   [ 31: 0] cpu_fpoint_s1_result;
  input            cpu_fpoint_s1_select;
  input            reset_n;

  wire             cpu_fpoint_s1_clk_en;
  wire    [ 31: 0] cpu_fpoint_s1_dataa;
  wire    [ 31: 0] cpu_fpoint_s1_datab;
  wire             cpu_fpoint_s1_done_from_sa;
  wire    [  1: 0] cpu_fpoint_s1_n;
  wire             cpu_fpoint_s1_reset;
  wire    [ 31: 0] cpu_fpoint_s1_result_from_sa;
  wire             cpu_fpoint_s1_start;
  assign cpu_fpoint_s1_clk_en = cpu_custom_instruction_master_multi_clk_en;
  assign cpu_fpoint_s1_dataa = cpu_custom_instruction_master_multi_dataa;
  assign cpu_fpoint_s1_datab = cpu_custom_instruction_master_multi_datab;
  assign cpu_fpoint_s1_n = cpu_custom_instruction_master_multi_n;
  assign cpu_fpoint_s1_start = cpu_custom_instruction_master_start_cpu_fpoint_s1;
  //assign cpu_fpoint_s1_result_from_sa = cpu_fpoint_s1_result so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cpu_fpoint_s1_result_from_sa = cpu_fpoint_s1_result;

  //assign cpu_fpoint_s1_done_from_sa = cpu_fpoint_s1_done so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cpu_fpoint_s1_done_from_sa = cpu_fpoint_s1_done;

  //cpu_fpoint/s1 local reset_n, which is an e_assign
  assign cpu_fpoint_s1_reset = ~reset_n;


endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module goIN_s1_arbitrator (
                            // inputs:
                             clk,
                             cpu_data_master_address_to_slave,
                             cpu_data_master_read,
                             cpu_data_master_write,
                             goIN_s1_readdata,
                             reset_n,

                            // outputs:
                             cpu_data_master_granted_goIN_s1,
                             cpu_data_master_qualified_request_goIN_s1,
                             cpu_data_master_read_data_valid_goIN_s1,
                             cpu_data_master_requests_goIN_s1,
                             d1_goIN_s1_end_xfer,
                             goIN_s1_address,
                             goIN_s1_readdata_from_sa,
                             goIN_s1_reset_n
                          )
;

  output           cpu_data_master_granted_goIN_s1;
  output           cpu_data_master_qualified_request_goIN_s1;
  output           cpu_data_master_read_data_valid_goIN_s1;
  output           cpu_data_master_requests_goIN_s1;
  output           d1_goIN_s1_end_xfer;
  output  [  1: 0] goIN_s1_address;
  output           goIN_s1_readdata_from_sa;
  output           goIN_s1_reset_n;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_write;
  input            goIN_s1_readdata;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_goIN_s1;
  wire             cpu_data_master_qualified_request_goIN_s1;
  wire             cpu_data_master_read_data_valid_goIN_s1;
  wire             cpu_data_master_requests_goIN_s1;
  wire             cpu_data_master_saved_grant_goIN_s1;
  reg              d1_goIN_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_goIN_s1;
  wire    [  1: 0] goIN_s1_address;
  wire             goIN_s1_allgrants;
  wire             goIN_s1_allow_new_arb_cycle;
  wire             goIN_s1_any_bursting_master_saved_grant;
  wire             goIN_s1_any_continuerequest;
  wire             goIN_s1_arb_counter_enable;
  reg     [  1: 0] goIN_s1_arb_share_counter;
  wire    [  1: 0] goIN_s1_arb_share_counter_next_value;
  wire    [  1: 0] goIN_s1_arb_share_set_values;
  wire             goIN_s1_beginbursttransfer_internal;
  wire             goIN_s1_begins_xfer;
  wire             goIN_s1_end_xfer;
  wire             goIN_s1_firsttransfer;
  wire             goIN_s1_grant_vector;
  wire             goIN_s1_in_a_read_cycle;
  wire             goIN_s1_in_a_write_cycle;
  wire             goIN_s1_master_qreq_vector;
  wire             goIN_s1_non_bursting_master_requests;
  wire             goIN_s1_readdata_from_sa;
  reg              goIN_s1_reg_firsttransfer;
  wire             goIN_s1_reset_n;
  reg              goIN_s1_slavearbiterlockenable;
  wire             goIN_s1_slavearbiterlockenable2;
  wire             goIN_s1_unreg_firsttransfer;
  wire             goIN_s1_waits_for_read;
  wire             goIN_s1_waits_for_write;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 24: 0] shifted_address_to_goIN_s1_from_cpu_data_master;
  wire             wait_for_goIN_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~goIN_s1_end_xfer;
    end


  assign goIN_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_goIN_s1));
  //assign goIN_s1_readdata_from_sa = goIN_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign goIN_s1_readdata_from_sa = goIN_s1_readdata;

  assign cpu_data_master_requests_goIN_s1 = (({cpu_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h1090) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_read;
  //goIN_s1_arb_share_counter set values, which is an e_mux
  assign goIN_s1_arb_share_set_values = 1;

  //goIN_s1_non_bursting_master_requests mux, which is an e_mux
  assign goIN_s1_non_bursting_master_requests = cpu_data_master_requests_goIN_s1;

  //goIN_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign goIN_s1_any_bursting_master_saved_grant = 0;

  //goIN_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign goIN_s1_arb_share_counter_next_value = goIN_s1_firsttransfer ? (goIN_s1_arb_share_set_values - 1) : |goIN_s1_arb_share_counter ? (goIN_s1_arb_share_counter - 1) : 0;

  //goIN_s1_allgrants all slave grants, which is an e_mux
  assign goIN_s1_allgrants = |goIN_s1_grant_vector;

  //goIN_s1_end_xfer assignment, which is an e_assign
  assign goIN_s1_end_xfer = ~(goIN_s1_waits_for_read | goIN_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_goIN_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_goIN_s1 = goIN_s1_end_xfer & (~goIN_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //goIN_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign goIN_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_goIN_s1 & goIN_s1_allgrants) | (end_xfer_arb_share_counter_term_goIN_s1 & ~goIN_s1_non_bursting_master_requests);

  //goIN_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          goIN_s1_arb_share_counter <= 0;
      else if (goIN_s1_arb_counter_enable)
          goIN_s1_arb_share_counter <= goIN_s1_arb_share_counter_next_value;
    end


  //goIN_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          goIN_s1_slavearbiterlockenable <= 0;
      else if ((|goIN_s1_master_qreq_vector & end_xfer_arb_share_counter_term_goIN_s1) | (end_xfer_arb_share_counter_term_goIN_s1 & ~goIN_s1_non_bursting_master_requests))
          goIN_s1_slavearbiterlockenable <= |goIN_s1_arb_share_counter_next_value;
    end


  //cpu/data_master goIN/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = goIN_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //goIN_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign goIN_s1_slavearbiterlockenable2 = |goIN_s1_arb_share_counter_next_value;

  //cpu/data_master goIN/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = goIN_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //goIN_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign goIN_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_goIN_s1 = cpu_data_master_requests_goIN_s1;
  //master is always granted when requested
  assign cpu_data_master_granted_goIN_s1 = cpu_data_master_qualified_request_goIN_s1;

  //cpu/data_master saved-grant goIN/s1, which is an e_assign
  assign cpu_data_master_saved_grant_goIN_s1 = cpu_data_master_requests_goIN_s1;

  //allow new arb cycle for goIN/s1, which is an e_assign
  assign goIN_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign goIN_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign goIN_s1_master_qreq_vector = 1;

  //goIN_s1_reset_n assignment, which is an e_assign
  assign goIN_s1_reset_n = reset_n;

  //goIN_s1_firsttransfer first transaction, which is an e_assign
  assign goIN_s1_firsttransfer = goIN_s1_begins_xfer ? goIN_s1_unreg_firsttransfer : goIN_s1_reg_firsttransfer;

  //goIN_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign goIN_s1_unreg_firsttransfer = ~(goIN_s1_slavearbiterlockenable & goIN_s1_any_continuerequest);

  //goIN_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          goIN_s1_reg_firsttransfer <= 1'b1;
      else if (goIN_s1_begins_xfer)
          goIN_s1_reg_firsttransfer <= goIN_s1_unreg_firsttransfer;
    end


  //goIN_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign goIN_s1_beginbursttransfer_internal = goIN_s1_begins_xfer;

  assign shifted_address_to_goIN_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //goIN_s1_address mux, which is an e_mux
  assign goIN_s1_address = shifted_address_to_goIN_s1_from_cpu_data_master >> 2;

  //d1_goIN_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_goIN_s1_end_xfer <= 1;
      else if (1)
          d1_goIN_s1_end_xfer <= goIN_s1_end_xfer;
    end


  //goIN_s1_waits_for_read in a cycle, which is an e_mux
  assign goIN_s1_waits_for_read = goIN_s1_in_a_read_cycle & goIN_s1_begins_xfer;

  //goIN_s1_in_a_read_cycle assignment, which is an e_assign
  assign goIN_s1_in_a_read_cycle = cpu_data_master_granted_goIN_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = goIN_s1_in_a_read_cycle;

  //goIN_s1_waits_for_write in a cycle, which is an e_mux
  assign goIN_s1_waits_for_write = goIN_s1_in_a_write_cycle & 0;

  //goIN_s1_in_a_write_cycle assignment, which is an e_assign
  assign goIN_s1_in_a_write_cycle = cpu_data_master_granted_goIN_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = goIN_s1_in_a_write_cycle;

  assign wait_for_goIN_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //goIN/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module goOUT_s1_arbitrator (
                             // inputs:
                              clk,
                              cpu_data_master_address_to_slave,
                              cpu_data_master_read,
                              cpu_data_master_waitrequest,
                              cpu_data_master_write,
                              cpu_data_master_writedata,
                              reset_n,

                             // outputs:
                              cpu_data_master_granted_goOUT_s1,
                              cpu_data_master_qualified_request_goOUT_s1,
                              cpu_data_master_read_data_valid_goOUT_s1,
                              cpu_data_master_requests_goOUT_s1,
                              d1_goOUT_s1_end_xfer,
                              goOUT_s1_address,
                              goOUT_s1_chipselect,
                              goOUT_s1_reset_n,
                              goOUT_s1_write_n,
                              goOUT_s1_writedata
                           )
;

  output           cpu_data_master_granted_goOUT_s1;
  output           cpu_data_master_qualified_request_goOUT_s1;
  output           cpu_data_master_read_data_valid_goOUT_s1;
  output           cpu_data_master_requests_goOUT_s1;
  output           d1_goOUT_s1_end_xfer;
  output  [  1: 0] goOUT_s1_address;
  output           goOUT_s1_chipselect;
  output           goOUT_s1_reset_n;
  output           goOUT_s1_write_n;
  output           goOUT_s1_writedata;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_goOUT_s1;
  wire             cpu_data_master_qualified_request_goOUT_s1;
  wire             cpu_data_master_read_data_valid_goOUT_s1;
  wire             cpu_data_master_requests_goOUT_s1;
  wire             cpu_data_master_saved_grant_goOUT_s1;
  reg              d1_goOUT_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_goOUT_s1;
  wire    [  1: 0] goOUT_s1_address;
  wire             goOUT_s1_allgrants;
  wire             goOUT_s1_allow_new_arb_cycle;
  wire             goOUT_s1_any_bursting_master_saved_grant;
  wire             goOUT_s1_any_continuerequest;
  wire             goOUT_s1_arb_counter_enable;
  reg     [  1: 0] goOUT_s1_arb_share_counter;
  wire    [  1: 0] goOUT_s1_arb_share_counter_next_value;
  wire    [  1: 0] goOUT_s1_arb_share_set_values;
  wire             goOUT_s1_beginbursttransfer_internal;
  wire             goOUT_s1_begins_xfer;
  wire             goOUT_s1_chipselect;
  wire             goOUT_s1_end_xfer;
  wire             goOUT_s1_firsttransfer;
  wire             goOUT_s1_grant_vector;
  wire             goOUT_s1_in_a_read_cycle;
  wire             goOUT_s1_in_a_write_cycle;
  wire             goOUT_s1_master_qreq_vector;
  wire             goOUT_s1_non_bursting_master_requests;
  reg              goOUT_s1_reg_firsttransfer;
  wire             goOUT_s1_reset_n;
  reg              goOUT_s1_slavearbiterlockenable;
  wire             goOUT_s1_slavearbiterlockenable2;
  wire             goOUT_s1_unreg_firsttransfer;
  wire             goOUT_s1_waits_for_read;
  wire             goOUT_s1_waits_for_write;
  wire             goOUT_s1_write_n;
  wire             goOUT_s1_writedata;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 24: 0] shifted_address_to_goOUT_s1_from_cpu_data_master;
  wire             wait_for_goOUT_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~goOUT_s1_end_xfer;
    end


  assign goOUT_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_goOUT_s1));
  assign cpu_data_master_requests_goOUT_s1 = (({cpu_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h1080) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_write;
  //goOUT_s1_arb_share_counter set values, which is an e_mux
  assign goOUT_s1_arb_share_set_values = 1;

  //goOUT_s1_non_bursting_master_requests mux, which is an e_mux
  assign goOUT_s1_non_bursting_master_requests = cpu_data_master_requests_goOUT_s1;

  //goOUT_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign goOUT_s1_any_bursting_master_saved_grant = 0;

  //goOUT_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign goOUT_s1_arb_share_counter_next_value = goOUT_s1_firsttransfer ? (goOUT_s1_arb_share_set_values - 1) : |goOUT_s1_arb_share_counter ? (goOUT_s1_arb_share_counter - 1) : 0;

  //goOUT_s1_allgrants all slave grants, which is an e_mux
  assign goOUT_s1_allgrants = |goOUT_s1_grant_vector;

  //goOUT_s1_end_xfer assignment, which is an e_assign
  assign goOUT_s1_end_xfer = ~(goOUT_s1_waits_for_read | goOUT_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_goOUT_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_goOUT_s1 = goOUT_s1_end_xfer & (~goOUT_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //goOUT_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign goOUT_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_goOUT_s1 & goOUT_s1_allgrants) | (end_xfer_arb_share_counter_term_goOUT_s1 & ~goOUT_s1_non_bursting_master_requests);

  //goOUT_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          goOUT_s1_arb_share_counter <= 0;
      else if (goOUT_s1_arb_counter_enable)
          goOUT_s1_arb_share_counter <= goOUT_s1_arb_share_counter_next_value;
    end


  //goOUT_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          goOUT_s1_slavearbiterlockenable <= 0;
      else if ((|goOUT_s1_master_qreq_vector & end_xfer_arb_share_counter_term_goOUT_s1) | (end_xfer_arb_share_counter_term_goOUT_s1 & ~goOUT_s1_non_bursting_master_requests))
          goOUT_s1_slavearbiterlockenable <= |goOUT_s1_arb_share_counter_next_value;
    end


  //cpu/data_master goOUT/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = goOUT_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //goOUT_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign goOUT_s1_slavearbiterlockenable2 = |goOUT_s1_arb_share_counter_next_value;

  //cpu/data_master goOUT/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = goOUT_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //goOUT_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign goOUT_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_goOUT_s1 = cpu_data_master_requests_goOUT_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //goOUT_s1_writedata mux, which is an e_mux
  assign goOUT_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_goOUT_s1 = cpu_data_master_qualified_request_goOUT_s1;

  //cpu/data_master saved-grant goOUT/s1, which is an e_assign
  assign cpu_data_master_saved_grant_goOUT_s1 = cpu_data_master_requests_goOUT_s1;

  //allow new arb cycle for goOUT/s1, which is an e_assign
  assign goOUT_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign goOUT_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign goOUT_s1_master_qreq_vector = 1;

  //goOUT_s1_reset_n assignment, which is an e_assign
  assign goOUT_s1_reset_n = reset_n;

  assign goOUT_s1_chipselect = cpu_data_master_granted_goOUT_s1;
  //goOUT_s1_firsttransfer first transaction, which is an e_assign
  assign goOUT_s1_firsttransfer = goOUT_s1_begins_xfer ? goOUT_s1_unreg_firsttransfer : goOUT_s1_reg_firsttransfer;

  //goOUT_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign goOUT_s1_unreg_firsttransfer = ~(goOUT_s1_slavearbiterlockenable & goOUT_s1_any_continuerequest);

  //goOUT_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          goOUT_s1_reg_firsttransfer <= 1'b1;
      else if (goOUT_s1_begins_xfer)
          goOUT_s1_reg_firsttransfer <= goOUT_s1_unreg_firsttransfer;
    end


  //goOUT_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign goOUT_s1_beginbursttransfer_internal = goOUT_s1_begins_xfer;

  //~goOUT_s1_write_n assignment, which is an e_mux
  assign goOUT_s1_write_n = ~(cpu_data_master_granted_goOUT_s1 & cpu_data_master_write);

  assign shifted_address_to_goOUT_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //goOUT_s1_address mux, which is an e_mux
  assign goOUT_s1_address = shifted_address_to_goOUT_s1_from_cpu_data_master >> 2;

  //d1_goOUT_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_goOUT_s1_end_xfer <= 1;
      else if (1)
          d1_goOUT_s1_end_xfer <= goOUT_s1_end_xfer;
    end


  //goOUT_s1_waits_for_read in a cycle, which is an e_mux
  assign goOUT_s1_waits_for_read = goOUT_s1_in_a_read_cycle & goOUT_s1_begins_xfer;

  //goOUT_s1_in_a_read_cycle assignment, which is an e_assign
  assign goOUT_s1_in_a_read_cycle = cpu_data_master_granted_goOUT_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = goOUT_s1_in_a_read_cycle;

  //goOUT_s1_waits_for_write in a cycle, which is an e_mux
  assign goOUT_s1_waits_for_write = goOUT_s1_in_a_write_cycle & 0;

  //goOUT_s1_in_a_write_cycle assignment, which is an e_assign
  assign goOUT_s1_in_a_write_cycle = cpu_data_master_granted_goOUT_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = goOUT_s1_in_a_write_cycle;

  assign wait_for_goOUT_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //goOUT/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module jtag_uart_avalon_jtag_slave_arbitrator (
                                                // inputs:
                                                 clk,
                                                 cpu_data_master_address_to_slave,
                                                 cpu_data_master_read,
                                                 cpu_data_master_waitrequest,
                                                 cpu_data_master_write,
                                                 cpu_data_master_writedata,
                                                 jtag_uart_avalon_jtag_slave_dataavailable,
                                                 jtag_uart_avalon_jtag_slave_irq,
                                                 jtag_uart_avalon_jtag_slave_readdata,
                                                 jtag_uart_avalon_jtag_slave_readyfordata,
                                                 jtag_uart_avalon_jtag_slave_waitrequest,
                                                 reset_n,

                                                // outputs:
                                                 cpu_data_master_granted_jtag_uart_avalon_jtag_slave,
                                                 cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave,
                                                 cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave,
                                                 cpu_data_master_requests_jtag_uart_avalon_jtag_slave,
                                                 d1_jtag_uart_avalon_jtag_slave_end_xfer,
                                                 jtag_uart_avalon_jtag_slave_address,
                                                 jtag_uart_avalon_jtag_slave_chipselect,
                                                 jtag_uart_avalon_jtag_slave_dataavailable_from_sa,
                                                 jtag_uart_avalon_jtag_slave_irq_from_sa,
                                                 jtag_uart_avalon_jtag_slave_read_n,
                                                 jtag_uart_avalon_jtag_slave_readdata_from_sa,
                                                 jtag_uart_avalon_jtag_slave_readyfordata_from_sa,
                                                 jtag_uart_avalon_jtag_slave_reset_n,
                                                 jtag_uart_avalon_jtag_slave_waitrequest_from_sa,
                                                 jtag_uart_avalon_jtag_slave_write_n,
                                                 jtag_uart_avalon_jtag_slave_writedata
                                              )
;

  output           cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
  output           cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
  output           cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
  output           cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
  output           d1_jtag_uart_avalon_jtag_slave_end_xfer;
  output           jtag_uart_avalon_jtag_slave_address;
  output           jtag_uart_avalon_jtag_slave_chipselect;
  output           jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
  output           jtag_uart_avalon_jtag_slave_irq_from_sa;
  output           jtag_uart_avalon_jtag_slave_read_n;
  output  [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
  output           jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
  output           jtag_uart_avalon_jtag_slave_reset_n;
  output           jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
  output           jtag_uart_avalon_jtag_slave_write_n;
  output  [ 31: 0] jtag_uart_avalon_jtag_slave_writedata;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            jtag_uart_avalon_jtag_slave_dataavailable;
  input            jtag_uart_avalon_jtag_slave_irq;
  input   [ 31: 0] jtag_uart_avalon_jtag_slave_readdata;
  input            jtag_uart_avalon_jtag_slave_readyfordata;
  input            jtag_uart_avalon_jtag_slave_waitrequest;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_saved_grant_jtag_uart_avalon_jtag_slave;
  reg              d1_jtag_uart_avalon_jtag_slave_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             jtag_uart_avalon_jtag_slave_address;
  wire             jtag_uart_avalon_jtag_slave_allgrants;
  wire             jtag_uart_avalon_jtag_slave_allow_new_arb_cycle;
  wire             jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant;
  wire             jtag_uart_avalon_jtag_slave_any_continuerequest;
  wire             jtag_uart_avalon_jtag_slave_arb_counter_enable;
  reg     [  1: 0] jtag_uart_avalon_jtag_slave_arb_share_counter;
  wire    [  1: 0] jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;
  wire    [  1: 0] jtag_uart_avalon_jtag_slave_arb_share_set_values;
  wire             jtag_uart_avalon_jtag_slave_beginbursttransfer_internal;
  wire             jtag_uart_avalon_jtag_slave_begins_xfer;
  wire             jtag_uart_avalon_jtag_slave_chipselect;
  wire             jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
  wire             jtag_uart_avalon_jtag_slave_end_xfer;
  wire             jtag_uart_avalon_jtag_slave_firsttransfer;
  wire             jtag_uart_avalon_jtag_slave_grant_vector;
  wire             jtag_uart_avalon_jtag_slave_in_a_read_cycle;
  wire             jtag_uart_avalon_jtag_slave_in_a_write_cycle;
  wire             jtag_uart_avalon_jtag_slave_irq_from_sa;
  wire             jtag_uart_avalon_jtag_slave_master_qreq_vector;
  wire             jtag_uart_avalon_jtag_slave_non_bursting_master_requests;
  wire             jtag_uart_avalon_jtag_slave_read_n;
  wire    [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
  wire             jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
  reg              jtag_uart_avalon_jtag_slave_reg_firsttransfer;
  wire             jtag_uart_avalon_jtag_slave_reset_n;
  reg              jtag_uart_avalon_jtag_slave_slavearbiterlockenable;
  wire             jtag_uart_avalon_jtag_slave_slavearbiterlockenable2;
  wire             jtag_uart_avalon_jtag_slave_unreg_firsttransfer;
  wire             jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
  wire             jtag_uart_avalon_jtag_slave_waits_for_read;
  wire             jtag_uart_avalon_jtag_slave_waits_for_write;
  wire             jtag_uart_avalon_jtag_slave_write_n;
  wire    [ 31: 0] jtag_uart_avalon_jtag_slave_writedata;
  wire    [ 24: 0] shifted_address_to_jtag_uart_avalon_jtag_slave_from_cpu_data_master;
  wire             wait_for_jtag_uart_avalon_jtag_slave_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~jtag_uart_avalon_jtag_slave_end_xfer;
    end


  assign jtag_uart_avalon_jtag_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave));
  //assign jtag_uart_avalon_jtag_slave_readdata_from_sa = jtag_uart_avalon_jtag_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_readdata_from_sa = jtag_uart_avalon_jtag_slave_readdata;

  assign cpu_data_master_requests_jtag_uart_avalon_jtag_slave = ({cpu_data_master_address_to_slave[24 : 3] , 3'b0} == 25'h10d0) & (cpu_data_master_read | cpu_data_master_write);
  //assign jtag_uart_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_avalon_jtag_slave_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_avalon_jtag_slave_dataavailable;

  //assign jtag_uart_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_avalon_jtag_slave_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_avalon_jtag_slave_readyfordata;

  //assign jtag_uart_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_avalon_jtag_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_avalon_jtag_slave_waitrequest;

  //jtag_uart_avalon_jtag_slave_arb_share_counter set values, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_arb_share_set_values = 1;

  //jtag_uart_avalon_jtag_slave_non_bursting_master_requests mux, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_non_bursting_master_requests = cpu_data_master_requests_jtag_uart_avalon_jtag_slave;

  //jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant mux, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant = 0;

  //jtag_uart_avalon_jtag_slave_arb_share_counter_next_value assignment, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_arb_share_counter_next_value = jtag_uart_avalon_jtag_slave_firsttransfer ? (jtag_uart_avalon_jtag_slave_arb_share_set_values - 1) : |jtag_uart_avalon_jtag_slave_arb_share_counter ? (jtag_uart_avalon_jtag_slave_arb_share_counter - 1) : 0;

  //jtag_uart_avalon_jtag_slave_allgrants all slave grants, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_allgrants = |jtag_uart_avalon_jtag_slave_grant_vector;

  //jtag_uart_avalon_jtag_slave_end_xfer assignment, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_end_xfer = ~(jtag_uart_avalon_jtag_slave_waits_for_read | jtag_uart_avalon_jtag_slave_waits_for_write);

  //end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave = jtag_uart_avalon_jtag_slave_end_xfer & (~jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //jtag_uart_avalon_jtag_slave_arb_share_counter arbitration counter enable, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave & jtag_uart_avalon_jtag_slave_allgrants) | (end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave & ~jtag_uart_avalon_jtag_slave_non_bursting_master_requests);

  //jtag_uart_avalon_jtag_slave_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          jtag_uart_avalon_jtag_slave_arb_share_counter <= 0;
      else if (jtag_uart_avalon_jtag_slave_arb_counter_enable)
          jtag_uart_avalon_jtag_slave_arb_share_counter <= jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;
    end


  //jtag_uart_avalon_jtag_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          jtag_uart_avalon_jtag_slave_slavearbiterlockenable <= 0;
      else if ((|jtag_uart_avalon_jtag_slave_master_qreq_vector & end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave) | (end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave & ~jtag_uart_avalon_jtag_slave_non_bursting_master_requests))
          jtag_uart_avalon_jtag_slave_slavearbiterlockenable <= |jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;
    end


  //cpu/data_master jtag_uart/avalon_jtag_slave arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = jtag_uart_avalon_jtag_slave_slavearbiterlockenable & cpu_data_master_continuerequest;

  //jtag_uart_avalon_jtag_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_slavearbiterlockenable2 = |jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;

  //cpu/data_master jtag_uart/avalon_jtag_slave arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = jtag_uart_avalon_jtag_slave_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //jtag_uart_avalon_jtag_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave = cpu_data_master_requests_jtag_uart_avalon_jtag_slave & ~((cpu_data_master_read & (~cpu_data_master_waitrequest)) | ((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //jtag_uart_avalon_jtag_slave_writedata mux, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_jtag_uart_avalon_jtag_slave = cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;

  //cpu/data_master saved-grant jtag_uart/avalon_jtag_slave, which is an e_assign
  assign cpu_data_master_saved_grant_jtag_uart_avalon_jtag_slave = cpu_data_master_requests_jtag_uart_avalon_jtag_slave;

  //allow new arb cycle for jtag_uart/avalon_jtag_slave, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign jtag_uart_avalon_jtag_slave_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign jtag_uart_avalon_jtag_slave_master_qreq_vector = 1;

  //jtag_uart_avalon_jtag_slave_reset_n assignment, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_reset_n = reset_n;

  assign jtag_uart_avalon_jtag_slave_chipselect = cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
  //jtag_uart_avalon_jtag_slave_firsttransfer first transaction, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_firsttransfer = jtag_uart_avalon_jtag_slave_begins_xfer ? jtag_uart_avalon_jtag_slave_unreg_firsttransfer : jtag_uart_avalon_jtag_slave_reg_firsttransfer;

  //jtag_uart_avalon_jtag_slave_unreg_firsttransfer first transaction, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_unreg_firsttransfer = ~(jtag_uart_avalon_jtag_slave_slavearbiterlockenable & jtag_uart_avalon_jtag_slave_any_continuerequest);

  //jtag_uart_avalon_jtag_slave_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          jtag_uart_avalon_jtag_slave_reg_firsttransfer <= 1'b1;
      else if (jtag_uart_avalon_jtag_slave_begins_xfer)
          jtag_uart_avalon_jtag_slave_reg_firsttransfer <= jtag_uart_avalon_jtag_slave_unreg_firsttransfer;
    end


  //jtag_uart_avalon_jtag_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_beginbursttransfer_internal = jtag_uart_avalon_jtag_slave_begins_xfer;

  //~jtag_uart_avalon_jtag_slave_read_n assignment, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_read_n = ~(cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_read);

  //~jtag_uart_avalon_jtag_slave_write_n assignment, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_write_n = ~(cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_write);

  assign shifted_address_to_jtag_uart_avalon_jtag_slave_from_cpu_data_master = cpu_data_master_address_to_slave;
  //jtag_uart_avalon_jtag_slave_address mux, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_address = shifted_address_to_jtag_uart_avalon_jtag_slave_from_cpu_data_master >> 2;

  //d1_jtag_uart_avalon_jtag_slave_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_jtag_uart_avalon_jtag_slave_end_xfer <= 1;
      else if (1)
          d1_jtag_uart_avalon_jtag_slave_end_xfer <= jtag_uart_avalon_jtag_slave_end_xfer;
    end


  //jtag_uart_avalon_jtag_slave_waits_for_read in a cycle, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_waits_for_read = jtag_uart_avalon_jtag_slave_in_a_read_cycle & jtag_uart_avalon_jtag_slave_waitrequest_from_sa;

  //jtag_uart_avalon_jtag_slave_in_a_read_cycle assignment, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_in_a_read_cycle = cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = jtag_uart_avalon_jtag_slave_in_a_read_cycle;

  //jtag_uart_avalon_jtag_slave_waits_for_write in a cycle, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_waits_for_write = jtag_uart_avalon_jtag_slave_in_a_write_cycle & jtag_uart_avalon_jtag_slave_waitrequest_from_sa;

  //jtag_uart_avalon_jtag_slave_in_a_write_cycle assignment, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_in_a_write_cycle = cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = jtag_uart_avalon_jtag_slave_in_a_write_cycle;

  assign wait_for_jtag_uart_avalon_jtag_slave_counter = 0;
  //assign jtag_uart_avalon_jtag_slave_irq_from_sa = jtag_uart_avalon_jtag_slave_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_irq_from_sa = jtag_uart_avalon_jtag_slave_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //jtag_uart/avalon_jtag_slave enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module onchip_mem_s1_arbitrator (
                                  // inputs:
                                   clk,
                                   cpu_data_master_address_to_slave,
                                   cpu_data_master_byteenable,
                                   cpu_data_master_dbs_address,
                                   cpu_data_master_dbs_write_16,
                                   cpu_data_master_no_byte_enables_and_last_term,
                                   cpu_data_master_read,
                                   cpu_data_master_waitrequest,
                                   cpu_data_master_write,
                                   cpu_instruction_master_address_to_slave,
                                   cpu_instruction_master_dbs_address,
                                   cpu_instruction_master_latency_counter,
                                   cpu_instruction_master_read,
                                   onchip_mem_s1_readdata,
                                   reset_n,

                                  // outputs:
                                   cpu_data_master_byteenable_onchip_mem_s1,
                                   cpu_data_master_granted_onchip_mem_s1,
                                   cpu_data_master_qualified_request_onchip_mem_s1,
                                   cpu_data_master_read_data_valid_onchip_mem_s1,
                                   cpu_data_master_requests_onchip_mem_s1,
                                   cpu_instruction_master_granted_onchip_mem_s1,
                                   cpu_instruction_master_qualified_request_onchip_mem_s1,
                                   cpu_instruction_master_read_data_valid_onchip_mem_s1,
                                   cpu_instruction_master_requests_onchip_mem_s1,
                                   d1_onchip_mem_s1_end_xfer,
                                   onchip_mem_s1_address,
                                   onchip_mem_s1_byteenable,
                                   onchip_mem_s1_chipselect,
                                   onchip_mem_s1_clken,
                                   onchip_mem_s1_readdata_from_sa,
                                   onchip_mem_s1_write,
                                   onchip_mem_s1_writedata,
                                   registered_cpu_data_master_read_data_valid_onchip_mem_s1
                                )
;

  output  [  1: 0] cpu_data_master_byteenable_onchip_mem_s1;
  output           cpu_data_master_granted_onchip_mem_s1;
  output           cpu_data_master_qualified_request_onchip_mem_s1;
  output           cpu_data_master_read_data_valid_onchip_mem_s1;
  output           cpu_data_master_requests_onchip_mem_s1;
  output           cpu_instruction_master_granted_onchip_mem_s1;
  output           cpu_instruction_master_qualified_request_onchip_mem_s1;
  output           cpu_instruction_master_read_data_valid_onchip_mem_s1;
  output           cpu_instruction_master_requests_onchip_mem_s1;
  output           d1_onchip_mem_s1_end_xfer;
  output  [ 12: 0] onchip_mem_s1_address;
  output  [  1: 0] onchip_mem_s1_byteenable;
  output           onchip_mem_s1_chipselect;
  output           onchip_mem_s1_clken;
  output  [ 15: 0] onchip_mem_s1_readdata_from_sa;
  output           onchip_mem_s1_write;
  output  [ 15: 0] onchip_mem_s1_writedata;
  output           registered_cpu_data_master_read_data_valid_onchip_mem_s1;
  input            clk;
  input   [ 24: 0] cpu_data_master_address_to_slave;
  input   [  3: 0] cpu_data_master_byteenable;
  input   [  1: 0] cpu_data_master_dbs_address;
  input   [ 15: 0] cpu_data_master_dbs_write_16;
  input            cpu_data_master_no_byte_enables_and_last_term;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 24: 0] cpu_instruction_master_address_to_slave;
  input   [  1: 0] cpu_instruction_master_dbs_address;
  input            cpu_instruction_master_latency_counter;
  input            cpu_instruction_master_read;
  input   [ 15: 0] onchip_mem_s1_readdata;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire    [  1: 0] cpu_data_master_byteenable_onchip_mem_s1;
  wire    [  1: 0] cpu_data_master_byteenable_onchip_mem_s1_segment_0;
  wire    [  1: 0] cpu_data_master_byteenable_onchip_mem_s1_segment_1;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_onchip_mem_s1;
  wire             cpu_data_master_qualified_request_onchip_mem_s1;
  wire             cpu_data_master_read_data_valid_onchip_mem_s1;
  reg              cpu_data_master_read_data_valid_onchip_mem_s1_shift_register;
  wire             cpu_data_master_read_data_valid_onchip_mem_s1_shift_register_in;
  wire             cpu_data_master_requests_onchip_mem_s1;
  wire             cpu_data_master_saved_grant_onchip_mem_s1;
  wire             cpu_instruction_master_arbiterlock;
  wire             cpu_instruction_master_arbiterlock2;
  wire             cpu_instruction_master_continuerequest;
  wire             cpu_instruction_master_granted_onchip_mem_s1;
  wire             cpu_instruction_master_qualified_request_onchip_mem_s1;
  wire             cpu_instruction_master_read_data_valid_onchip_mem_s1;
  reg              cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register;
  wire             cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register_in;
  wire             cpu_instruction_master_requests_onchip_mem_s1;
  wire             cpu_instruction_master_saved_grant_onchip_mem_s1;
  reg              d1_onchip_mem_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_onchip_mem_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_cpu_data_master_granted_slave_onchip_mem_s1;
  reg              last_cycle_cpu_instruction_master_granted_slave_onchip_mem_s1;
  wire    [ 12: 0] onchip_mem_s1_address;
  wire             onchip_mem_s1_allgrants;
  wire             onchip_mem_s1_allow_new_arb_cycle;
  wire             onchip_mem_s1_any_bursting_master_saved_grant;
  wire             onchip_mem_s1_any_continuerequest;
  reg     [  1: 0] onchip_mem_s1_arb_addend;
  wire             onchip_mem_s1_arb_counter_enable;
  reg     [  1: 0] onchip_mem_s1_arb_share_counter;
  wire    [  1: 0] onchip_mem_s1_arb_share_counter_next_value;
  wire    [  1: 0] onchip_mem_s1_arb_share_set_values;
  wire    [  1: 0] onchip_mem_s1_arb_winner;
  wire             onchip_mem_s1_arbitration_holdoff_internal;
  wire             onchip_mem_s1_beginbursttransfer_internal;
  wire             onchip_mem_s1_begins_xfer;
  wire    [  1: 0] onchip_mem_s1_byteenable;
  wire             onchip_mem_s1_chipselect;
  wire    [  3: 0] onchip_mem_s1_chosen_master_double_vector;
  wire    [  1: 0] onchip_mem_s1_chosen_master_rot_left;
  wire             onchip_mem_s1_clken;
  wire             onchip_mem_s1_end_xfer;
  wire             onchip_mem_s1_firsttransfer;
  wire    [  1: 0] onchip_mem_s1_grant_vector;
  wire             onchip_mem_s1_in_a_read_cycle;
  wire             onchip_mem_s1_in_a_write_cycle;
  wire    [  1: 0] onchip_mem_s1_master_qreq_vector;
  wire             onchip_mem_s1_non_bursting_master_requests;
  wire    [ 15: 0] onchip_mem_s1_readdata_from_sa;
  reg              onchip_mem_s1_reg_firsttransfer;
  reg     [  1: 0] onchip_mem_s1_saved_chosen_master_vector;
  reg              onchip_mem_s1_slavearbiterlockenable;
  wire             onchip_mem_s1_slavearbiterlockenable2;
  wire             onchip_mem_s1_unreg_firsttransfer;
  wire             onchip_mem_s1_waits_for_read;
  wire             onchip_mem_s1_waits_for_write;
  wire             onchip_mem_s1_write;
  wire    [ 15: 0] onchip_mem_s1_writedata;
  wire             p1_cpu_data_master_read_data_valid_onchip_mem_s1_shift_register;
  wire             p1_cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register;
  wire             registered_cpu_data_master_read_data_valid_onchip_mem_s1;
  wire    [ 24: 0] shifted_address_to_onchip_mem_s1_from_cpu_data_master;
  wire    [ 24: 0] shifted_address_to_onchip_mem_s1_from_cpu_instruction_master;
  wire             wait_for_onchip_mem_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~onchip_mem_s1_end_xfer;
    end


  assign onchip_mem_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_onchip_mem_s1 | cpu_instruction_master_qualified_request_onchip_mem_s1));
  //assign onchip_mem_s1_readdata_from_sa = onchip_mem_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign onchip_mem_s1_readdata_from_sa = onchip_mem_s1_readdata;

  assign cpu_data_master_requests_onchip_mem_s1 = ({cpu_data_master_address_to_slave[24 : 14] , 14'b0} == 25'h1000000) & (cpu_data_master_read | cpu_data_master_write);
  //registered rdv signal_name registered_cpu_data_master_read_data_valid_onchip_mem_s1 assignment, which is an e_assign
  assign registered_cpu_data_master_read_data_valid_onchip_mem_s1 = cpu_data_master_read_data_valid_onchip_mem_s1_shift_register_in;

  //onchip_mem_s1_arb_share_counter set values, which is an e_mux
  assign onchip_mem_s1_arb_share_set_values = (cpu_data_master_granted_onchip_mem_s1)? 2 :
    (cpu_instruction_master_granted_onchip_mem_s1)? 2 :
    (cpu_data_master_granted_onchip_mem_s1)? 2 :
    (cpu_instruction_master_granted_onchip_mem_s1)? 2 :
    1;

  //onchip_mem_s1_non_bursting_master_requests mux, which is an e_mux
  assign onchip_mem_s1_non_bursting_master_requests = cpu_data_master_requests_onchip_mem_s1 |
    cpu_instruction_master_requests_onchip_mem_s1 |
    cpu_data_master_requests_onchip_mem_s1 |
    cpu_instruction_master_requests_onchip_mem_s1;

  //onchip_mem_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign onchip_mem_s1_any_bursting_master_saved_grant = 0;

  //onchip_mem_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign onchip_mem_s1_arb_share_counter_next_value = onchip_mem_s1_firsttransfer ? (onchip_mem_s1_arb_share_set_values - 1) : |onchip_mem_s1_arb_share_counter ? (onchip_mem_s1_arb_share_counter - 1) : 0;

  //onchip_mem_s1_allgrants all slave grants, which is an e_mux
  assign onchip_mem_s1_allgrants = |onchip_mem_s1_grant_vector |
    |onchip_mem_s1_grant_vector |
    |onchip_mem_s1_grant_vector |
    |onchip_mem_s1_grant_vector;

  //onchip_mem_s1_end_xfer assignment, which is an e_assign
  assign onchip_mem_s1_end_xfer = ~(onchip_mem_s1_waits_for_read | onchip_mem_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_onchip_mem_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_onchip_mem_s1 = onchip_mem_s1_end_xfer & (~onchip_mem_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //onchip_mem_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign onchip_mem_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_onchip_mem_s1 & onchip_mem_s1_allgrants) | (end_xfer_arb_share_counter_term_onchip_mem_s1 & ~onchip_mem_s1_non_bursting_master_requests);

  //onchip_mem_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          onchip_mem_s1_arb_share_counter <= 0;
      else if (onchip_mem_s1_arb_counter_enable)
          onchip_mem_s1_arb_share_counter <= onchip_mem_s1_arb_share_counter_next_value;
    end


  //onchip_mem_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          onchip_mem_s1_slavearbiterlockenable <= 0;
      else if ((|onchip_mem_s1_master_qreq_vector & end_xfer_arb_share_counter_term_onchip_mem_s1) | (end_xfer_arb_share_counter_term_onchip_mem_s1 & ~onchip_mem_s1_non_bursting_master_requests))
          onchip_mem_s1_slavearbiterlockenable <= |onchip_mem_s1_arb_share_counter_next_value;
    end


  //cpu/data_master onchip_mem/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = onchip_mem_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //onchip_mem_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign onchip_mem_s1_slavearbiterlockenable2 = |onchip_mem_s1_arb_share_counter_next_value;

  //cpu/data_master onchip_mem/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = onchip_mem_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //cpu/instruction_master onchip_mem/s1 arbiterlock, which is an e_assign
  assign cpu_instruction_master_arbiterlock = onchip_mem_s1_slavearbiterlockenable & cpu_instruction_master_continuerequest;

  //cpu/instruction_master onchip_mem/s1 arbiterlock2, which is an e_assign
  assign cpu_instruction_master_arbiterlock2 = onchip_mem_s1_slavearbiterlockenable2 & cpu_instruction_master_continuerequest;

  //cpu/instruction_master granted onchip_mem/s1 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_instruction_master_granted_slave_onchip_mem_s1 <= 0;
      else if (1)
          last_cycle_cpu_instruction_master_granted_slave_onchip_mem_s1 <= cpu_instruction_master_saved_grant_onchip_mem_s1 ? 1 : (onchip_mem_s1_arbitration_holdoff_internal | ~cpu_instruction_master_requests_onchip_mem_s1) ? 0 : last_cycle_cpu_instruction_master_granted_slave_onchip_mem_s1;
    end


  //cpu_instruction_master_continuerequest continued request, which is an e_mux
  assign cpu_instruction_master_continuerequest = last_cycle_cpu_instruction_master_granted_slave_onchip_mem_s1 & cpu_instruction_master_requests_onchip_mem_s1;

  //onchip_mem_s1_any_continuerequest at least one master continues requesting, which is an e_mux
  assign onchip_mem_s1_any_continuerequest = cpu_instruction_master_continuerequest |
    cpu_data_master_continuerequest;

  assign cpu_data_master_qualified_request_onchip_mem_s1 = cpu_data_master_requests_onchip_mem_s1 & ~((cpu_data_master_read & ((|cpu_data_master_read_data_valid_onchip_mem_s1_shift_register))) | ((~cpu_data_master_waitrequest | cpu_data_master_no_byte_enables_and_last_term | !cpu_data_master_byteenable_onchip_mem_s1) & cpu_data_master_write) | cpu_instruction_master_arbiterlock);
  //cpu_data_master_read_data_valid_onchip_mem_s1_shift_register_in mux for readlatency shift register, which is an e_mux
  assign cpu_data_master_read_data_valid_onchip_mem_s1_shift_register_in = cpu_data_master_granted_onchip_mem_s1 & cpu_data_master_read & ~onchip_mem_s1_waits_for_read & ~(|cpu_data_master_read_data_valid_onchip_mem_s1_shift_register);

  //shift register p1 cpu_data_master_read_data_valid_onchip_mem_s1_shift_register in if flush, otherwise shift left, which is an e_mux
  assign p1_cpu_data_master_read_data_valid_onchip_mem_s1_shift_register = {cpu_data_master_read_data_valid_onchip_mem_s1_shift_register, cpu_data_master_read_data_valid_onchip_mem_s1_shift_register_in};

  //cpu_data_master_read_data_valid_onchip_mem_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_read_data_valid_onchip_mem_s1_shift_register <= 0;
      else if (1)
          cpu_data_master_read_data_valid_onchip_mem_s1_shift_register <= p1_cpu_data_master_read_data_valid_onchip_mem_s1_shift_register;
    end


  //local readdatavalid cpu_data_master_read_data_valid_onchip_mem_s1, which is an e_mux
  assign cpu_data_master_read_data_valid_onchip_mem_s1 = cpu_data_master_read_data_valid_onchip_mem_s1_shift_register;

  //onchip_mem_s1_writedata mux, which is an e_mux
  assign onchip_mem_s1_writedata = cpu_data_master_dbs_write_16;

  //mux onchip_mem_s1_clken, which is an e_mux
  assign onchip_mem_s1_clken = 1'b1;

  assign cpu_instruction_master_requests_onchip_mem_s1 = (({cpu_instruction_master_address_to_slave[24 : 14] , 14'b0} == 25'h1000000) & (cpu_instruction_master_read)) & cpu_instruction_master_read;
  //cpu/data_master granted onchip_mem/s1 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_data_master_granted_slave_onchip_mem_s1 <= 0;
      else if (1)
          last_cycle_cpu_data_master_granted_slave_onchip_mem_s1 <= cpu_data_master_saved_grant_onchip_mem_s1 ? 1 : (onchip_mem_s1_arbitration_holdoff_internal | ~cpu_data_master_requests_onchip_mem_s1) ? 0 : last_cycle_cpu_data_master_granted_slave_onchip_mem_s1;
    end


  //cpu_data_master_continuerequest continued request, which is an e_mux
  assign cpu_data_master_continuerequest = last_cycle_cpu_data_master_granted_slave_onchip_mem_s1 & cpu_data_master_requests_onchip_mem_s1;

  assign cpu_instruction_master_qualified_request_onchip_mem_s1 = cpu_instruction_master_requests_onchip_mem_s1 & ~((cpu_instruction_master_read & ((1 < cpu_instruction_master_latency_counter))) | cpu_data_master_arbiterlock);
  //cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register_in mux for readlatency shift register, which is an e_mux
  assign cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register_in = cpu_instruction_master_granted_onchip_mem_s1 & cpu_instruction_master_read & ~onchip_mem_s1_waits_for_read;

  //shift register p1 cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register in if flush, otherwise shift left, which is an e_mux
  assign p1_cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register = {cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register, cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register_in};

  //cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register <= 0;
      else if (1)
          cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register <= p1_cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register;
    end


  //local readdatavalid cpu_instruction_master_read_data_valid_onchip_mem_s1, which is an e_mux
  assign cpu_instruction_master_read_data_valid_onchip_mem_s1 = cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register;

  //allow new arb cycle for onchip_mem/s1, which is an e_assign
  assign onchip_mem_s1_allow_new_arb_cycle = ~cpu_data_master_arbiterlock & ~cpu_instruction_master_arbiterlock;

  //cpu/instruction_master assignment into master qualified-requests vector for onchip_mem/s1, which is an e_assign
  assign onchip_mem_s1_master_qreq_vector[0] = cpu_instruction_master_qualified_request_onchip_mem_s1;

  //cpu/instruction_master grant onchip_mem/s1, which is an e_assign
  assign cpu_instruction_master_granted_onchip_mem_s1 = onchip_mem_s1_grant_vector[0];

  //cpu/instruction_master saved-grant onchip_mem/s1, which is an e_assign
  assign cpu_instruction_master_saved_grant_onchip_mem_s1 = onchip_mem_s1_arb_winner[0] && cpu_instruction_master_requests_onchip_mem_s1;

  //cpu/data_master assignment into master qualified-requests vector for onchip_mem/s1, which is an e_assign
  assign onchip_mem_s1_master_qreq_vector[1] = cpu_data_master_qualified_request_onchip_mem_s1;

  //cpu/data_master grant onchip_mem/s1, which is an e_assign
  assign cpu_data_master_granted_onchip_mem_s1 = onchip_mem_s1_grant_vector[1];

  //cpu/data_master saved-grant onchip_mem/s1, which is an e_assign
  assign cpu_data_master_saved_grant_onchip_mem_s1 = onchip_mem_s1_arb_winner[1] && cpu_data_master_requests_onchip_mem_s1;

  //onchip_mem/s1 chosen-master double-vector, which is an e_assign
  assign onchip_mem_s1_chosen_master_double_vector = {onchip_mem_s1_master_qreq_vector, onchip_mem_s1_master_qreq_vector} & ({~onchip_mem_s1_master_qreq_vector, ~onchip_mem_s1_master_qreq_vector} + onchip_mem_s1_arb_addend);

  //stable onehot encoding of arb winner
  assign onchip_mem_s1_arb_winner = (onchip_mem_s1_allow_new_arb_cycle & | onchip_mem_s1_grant_vector) ? onchip_mem_s1_grant_vector : onchip_mem_s1_saved_chosen_master_vector;

  //saved onchip_mem_s1_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          onchip_mem_s1_saved_chosen_master_vector <= 0;
      else if (onchip_mem_s1_allow_new_arb_cycle)
          onchip_mem_s1_saved_chosen_master_vector <= |onchip_mem_s1_grant_vector ? onchip_mem_s1_grant_vector : onchip_mem_s1_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign onchip_mem_s1_grant_vector = {(onchip_mem_s1_chosen_master_double_vector[1] | onchip_mem_s1_chosen_master_double_vector[3]),
    (onchip_mem_s1_chosen_master_double_vector[0] | onchip_mem_s1_chosen_master_double_vector[2])};

  //onchip_mem/s1 chosen master rotated left, which is an e_assign
  assign onchip_mem_s1_chosen_master_rot_left = (onchip_mem_s1_arb_winner << 1) ? (onchip_mem_s1_arb_winner << 1) : 1;

  //onchip_mem/s1's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          onchip_mem_s1_arb_addend <= 1;
      else if (|onchip_mem_s1_grant_vector)
          onchip_mem_s1_arb_addend <= onchip_mem_s1_end_xfer? onchip_mem_s1_chosen_master_rot_left : onchip_mem_s1_grant_vector;
    end


  assign onchip_mem_s1_chipselect = cpu_data_master_granted_onchip_mem_s1 | cpu_instruction_master_granted_onchip_mem_s1;
  //onchip_mem_s1_firsttransfer first transaction, which is an e_assign
  assign onchip_mem_s1_firsttransfer = onchip_mem_s1_begins_xfer ? onchip_mem_s1_unreg_firsttransfer : onchip_mem_s1_reg_firsttransfer;

  //onchip_mem_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign onchip_mem_s1_unreg_firsttransfer = ~(onchip_mem_s1_slavearbiterlockenable & onchip_mem_s1_any_continuerequest);

  //onchip_mem_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          onchip_mem_s1_reg_firsttransfer <= 1'b1;
      else if (onchip_mem_s1_begins_xfer)
          onchip_mem_s1_reg_firsttransfer <= onchip_mem_s1_unreg_firsttransfer;
    end


  //onchip_mem_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign onchip_mem_s1_beginbursttransfer_internal = onchip_mem_s1_begins_xfer;

  //onchip_mem_s1_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign onchip_mem_s1_arbitration_holdoff_internal = onchip_mem_s1_begins_xfer & onchip_mem_s1_firsttransfer;

  //onchip_mem_s1_write assignment, which is an e_mux
  assign onchip_mem_s1_write = cpu_data_master_granted_onchip_mem_s1 & cpu_data_master_write;

  assign shifted_address_to_onchip_mem_s1_from_cpu_data_master = {cpu_data_master_address_to_slave >> 2,
    cpu_data_master_dbs_address[1],
    {1 {1'b0}}};

  //onchip_mem_s1_address mux, which is an e_mux
  assign onchip_mem_s1_address = (cpu_data_master_granted_onchip_mem_s1)? (shifted_address_to_onchip_mem_s1_from_cpu_data_master >> 1) :
    (shifted_address_to_onchip_mem_s1_from_cpu_instruction_master >> 1);

  assign shifted_address_to_onchip_mem_s1_from_cpu_instruction_master = {cpu_instruction_master_address_to_slave >> 2,
    cpu_instruction_master_dbs_address[1],
    {1 {1'b0}}};

  //d1_onchip_mem_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_onchip_mem_s1_end_xfer <= 1;
      else if (1)
          d1_onchip_mem_s1_end_xfer <= onchip_mem_s1_end_xfer;
    end


  //onchip_mem_s1_waits_for_read in a cycle, which is an e_mux
  assign onchip_mem_s1_waits_for_read = onchip_mem_s1_in_a_read_cycle & 0;

  //onchip_mem_s1_in_a_read_cycle assignment, which is an e_assign
  assign onchip_mem_s1_in_a_read_cycle = (cpu_data_master_granted_onchip_mem_s1 & cpu_data_master_read) | (cpu_instruction_master_granted_onchip_mem_s1 & cpu_instruction_master_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = onchip_mem_s1_in_a_read_cycle;

  //onchip_mem_s1_waits_for_write in a cycle, which is an e_mux
  assign onchip_mem_s1_waits_for_write = onchip_mem_s1_in_a_write_cycle & 0;

  //onchip_mem_s1_in_a_write_cycle assignment, which is an e_assign
  assign onchip_mem_s1_in_a_write_cycle = cpu_data_master_granted_onchip_mem_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = onchip_mem_s1_in_a_write_cycle;

  assign wait_for_onchip_mem_s1_counter = 0;
  //onchip_mem_s1_byteenable byte enable port mux, which is an e_mux
  assign onchip_mem_s1_byteenable = (cpu_data_master_granted_onchip_mem_s1)? cpu_data_master_byteenable_onchip_mem_s1 :
    -1;

  assign {cpu_data_master_byteenable_onchip_mem_s1_segment_1,
cpu_data_master_byteenable_onchip_mem_s1_segment_0} = cpu_data_master_byteenable;
  assign cpu_data_master_byteenable_onchip_mem_s1 = ((cpu_data_master_dbs_address[1] == 0))? cpu_data_master_byteenable_onchip_mem_s1_segment_0 :
    cpu_data_master_byteenable_onchip_mem_s1_segment_1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //onchip_mem/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end


  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_granted_onchip_mem_s1 + cpu_instruction_master_granted_onchip_mem_s1 > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_saved_grant_onchip_mem_s1 + cpu_instruction_master_saved_grant_onchip_mem_s1 > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module projection_reset_clk_domain_synch_module (
                                                  // inputs:
                                                   clk,
                                                   data_in,
                                                   reset_n,

                                                  // outputs:
                                                   data_out
                                                )
;

  output           data_out;
  input            clk;
  input            data_in;
  input            reset_n;

  reg              data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101"  */;
  reg              data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101"  */;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          data_in_d1 <= 0;
      else if (1)
          data_in_d1 <= data_in;
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          data_out <= 0;
      else if (1)
          data_out <= data_in_d1;
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module projection (
                    // 1) global signals:
                     clk,
                     reset_n,

                    // the_AREA
                     in_port_to_the_AREA,

                    // the_B1
                     out_port_from_the_B1,

                    // the_B2
                     out_port_from_the_B2,

                    // the_B3
                     out_port_from_the_B3,

                    // the_B4
                     out_port_from_the_B4,

                    // the_B5
                     out_port_from_the_B5,

                    // the_B6
                     out_port_from_the_B6,

                    // the_B7
                     out_port_from_the_B7,

                    // the_B8
                     out_port_from_the_B8,

                    // the_RESET
                     in_port_to_the_RESET,

                    // the_XOFF
                     in_port_to_the_XOFF,

                    // the_YOFF
                     in_port_to_the_YOFF,

                    // the_goIN
                     in_port_to_the_goIN,

                    // the_goOUT
                     out_port_from_the_goOUT
                  )
;

  output  [ 17: 0] out_port_from_the_B1;
  output  [ 17: 0] out_port_from_the_B2;
  output  [ 17: 0] out_port_from_the_B3;
  output  [ 17: 0] out_port_from_the_B4;
  output  [ 17: 0] out_port_from_the_B5;
  output  [ 17: 0] out_port_from_the_B6;
  output  [ 17: 0] out_port_from_the_B7;
  output  [ 17: 0] out_port_from_the_B8;
  output           out_port_from_the_goOUT;
  input            clk;
  input   [ 31: 0] in_port_to_the_AREA;
  input            in_port_to_the_RESET;
  input   [  8: 0] in_port_to_the_XOFF;
  input   [  8: 0] in_port_to_the_YOFF;
  input            in_port_to_the_goIN;
  input            reset_n;

  wire    [  1: 0] AREA_s1_address;
  wire    [ 31: 0] AREA_s1_readdata;
  wire    [ 31: 0] AREA_s1_readdata_from_sa;
  wire             AREA_s1_reset_n;
  wire    [  1: 0] B1_s1_address;
  wire             B1_s1_chipselect;
  wire             B1_s1_reset_n;
  wire             B1_s1_write_n;
  wire    [ 17: 0] B1_s1_writedata;
  wire    [  1: 0] B2_s1_address;
  wire             B2_s1_chipselect;
  wire             B2_s1_reset_n;
  wire             B2_s1_write_n;
  wire    [ 17: 0] B2_s1_writedata;
  wire    [  1: 0] B3_s1_address;
  wire             B3_s1_chipselect;
  wire             B3_s1_reset_n;
  wire             B3_s1_write_n;
  wire    [ 17: 0] B3_s1_writedata;
  wire    [  1: 0] B4_s1_address;
  wire             B4_s1_chipselect;
  wire             B4_s1_reset_n;
  wire             B4_s1_write_n;
  wire    [ 17: 0] B4_s1_writedata;
  wire    [  1: 0] B5_s1_address;
  wire             B5_s1_chipselect;
  wire             B5_s1_reset_n;
  wire             B5_s1_write_n;
  wire    [ 17: 0] B5_s1_writedata;
  wire    [  1: 0] B6_s1_address;
  wire             B6_s1_chipselect;
  wire             B6_s1_reset_n;
  wire             B6_s1_write_n;
  wire    [ 17: 0] B6_s1_writedata;
  wire    [  1: 0] B7_s1_address;
  wire             B7_s1_chipselect;
  wire             B7_s1_reset_n;
  wire             B7_s1_write_n;
  wire    [ 17: 0] B7_s1_writedata;
  wire    [  1: 0] B8_s1_address;
  wire             B8_s1_chipselect;
  wire             B8_s1_reset_n;
  wire             B8_s1_write_n;
  wire    [ 17: 0] B8_s1_writedata;
  wire    [  1: 0] RESET_s1_address;
  wire             RESET_s1_readdata;
  wire             RESET_s1_readdata_from_sa;
  wire             RESET_s1_reset_n;
  wire    [  1: 0] XOFF_s1_address;
  wire    [  8: 0] XOFF_s1_readdata;
  wire    [  8: 0] XOFF_s1_readdata_from_sa;
  wire             XOFF_s1_reset_n;
  wire    [  1: 0] YOFF_s1_address;
  wire    [  8: 0] YOFF_s1_readdata;
  wire    [  8: 0] YOFF_s1_readdata_from_sa;
  wire             YOFF_s1_reset_n;
  wire             clk_reset_n;
  wire    [  4: 0] cpu_custom_instruction_master_multi_a;
  wire    [  4: 0] cpu_custom_instruction_master_multi_b;
  wire    [  4: 0] cpu_custom_instruction_master_multi_c;
  wire             cpu_custom_instruction_master_multi_clk_en;
  wire    [ 31: 0] cpu_custom_instruction_master_multi_dataa;
  wire    [ 31: 0] cpu_custom_instruction_master_multi_datab;
  wire             cpu_custom_instruction_master_multi_done;
  wire             cpu_custom_instruction_master_multi_estatus;
  wire    [ 31: 0] cpu_custom_instruction_master_multi_ipending;
  wire    [  7: 0] cpu_custom_instruction_master_multi_n;
  wire             cpu_custom_instruction_master_multi_readra;
  wire             cpu_custom_instruction_master_multi_readrb;
  wire    [ 31: 0] cpu_custom_instruction_master_multi_result;
  wire             cpu_custom_instruction_master_multi_start;
  wire             cpu_custom_instruction_master_multi_status;
  wire             cpu_custom_instruction_master_multi_writerc;
  wire             cpu_custom_instruction_master_reset_n;
  wire             cpu_custom_instruction_master_start_cpu_fpoint_s1;
  wire    [ 24: 0] cpu_data_master_address;
  wire    [ 24: 0] cpu_data_master_address_to_slave;
  wire    [  3: 0] cpu_data_master_byteenable;
  wire    [  1: 0] cpu_data_master_byteenable_onchip_mem_s1;
  wire    [  1: 0] cpu_data_master_dbs_address;
  wire    [ 15: 0] cpu_data_master_dbs_write_16;
  wire             cpu_data_master_debugaccess;
  wire             cpu_data_master_granted_AREA_s1;
  wire             cpu_data_master_granted_B1_s1;
  wire             cpu_data_master_granted_B2_s1;
  wire             cpu_data_master_granted_B3_s1;
  wire             cpu_data_master_granted_B4_s1;
  wire             cpu_data_master_granted_B5_s1;
  wire             cpu_data_master_granted_B6_s1;
  wire             cpu_data_master_granted_B7_s1;
  wire             cpu_data_master_granted_B8_s1;
  wire             cpu_data_master_granted_RESET_s1;
  wire             cpu_data_master_granted_XOFF_s1;
  wire             cpu_data_master_granted_YOFF_s1;
  wire             cpu_data_master_granted_cpu_jtag_debug_module;
  wire             cpu_data_master_granted_goIN_s1;
  wire             cpu_data_master_granted_goOUT_s1;
  wire             cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_granted_onchip_mem_s1;
  wire    [ 31: 0] cpu_data_master_irq;
  wire             cpu_data_master_no_byte_enables_and_last_term;
  wire             cpu_data_master_qualified_request_AREA_s1;
  wire             cpu_data_master_qualified_request_B1_s1;
  wire             cpu_data_master_qualified_request_B2_s1;
  wire             cpu_data_master_qualified_request_B3_s1;
  wire             cpu_data_master_qualified_request_B4_s1;
  wire             cpu_data_master_qualified_request_B5_s1;
  wire             cpu_data_master_qualified_request_B6_s1;
  wire             cpu_data_master_qualified_request_B7_s1;
  wire             cpu_data_master_qualified_request_B8_s1;
  wire             cpu_data_master_qualified_request_RESET_s1;
  wire             cpu_data_master_qualified_request_XOFF_s1;
  wire             cpu_data_master_qualified_request_YOFF_s1;
  wire             cpu_data_master_qualified_request_cpu_jtag_debug_module;
  wire             cpu_data_master_qualified_request_goIN_s1;
  wire             cpu_data_master_qualified_request_goOUT_s1;
  wire             cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_qualified_request_onchip_mem_s1;
  wire             cpu_data_master_read;
  wire             cpu_data_master_read_data_valid_AREA_s1;
  wire             cpu_data_master_read_data_valid_B1_s1;
  wire             cpu_data_master_read_data_valid_B2_s1;
  wire             cpu_data_master_read_data_valid_B3_s1;
  wire             cpu_data_master_read_data_valid_B4_s1;
  wire             cpu_data_master_read_data_valid_B5_s1;
  wire             cpu_data_master_read_data_valid_B6_s1;
  wire             cpu_data_master_read_data_valid_B7_s1;
  wire             cpu_data_master_read_data_valid_B8_s1;
  wire             cpu_data_master_read_data_valid_RESET_s1;
  wire             cpu_data_master_read_data_valid_XOFF_s1;
  wire             cpu_data_master_read_data_valid_YOFF_s1;
  wire             cpu_data_master_read_data_valid_cpu_jtag_debug_module;
  wire             cpu_data_master_read_data_valid_goIN_s1;
  wire             cpu_data_master_read_data_valid_goOUT_s1;
  wire             cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_read_data_valid_onchip_mem_s1;
  wire    [ 31: 0] cpu_data_master_readdata;
  wire             cpu_data_master_requests_AREA_s1;
  wire             cpu_data_master_requests_B1_s1;
  wire             cpu_data_master_requests_B2_s1;
  wire             cpu_data_master_requests_B3_s1;
  wire             cpu_data_master_requests_B4_s1;
  wire             cpu_data_master_requests_B5_s1;
  wire             cpu_data_master_requests_B6_s1;
  wire             cpu_data_master_requests_B7_s1;
  wire             cpu_data_master_requests_B8_s1;
  wire             cpu_data_master_requests_RESET_s1;
  wire             cpu_data_master_requests_XOFF_s1;
  wire             cpu_data_master_requests_YOFF_s1;
  wire             cpu_data_master_requests_cpu_jtag_debug_module;
  wire             cpu_data_master_requests_goIN_s1;
  wire             cpu_data_master_requests_goOUT_s1;
  wire             cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_requests_onchip_mem_s1;
  wire             cpu_data_master_waitrequest;
  wire             cpu_data_master_write;
  wire    [ 31: 0] cpu_data_master_writedata;
  wire             cpu_fpoint_s1_clk_en;
  wire    [ 31: 0] cpu_fpoint_s1_dataa;
  wire    [ 31: 0] cpu_fpoint_s1_datab;
  wire             cpu_fpoint_s1_done;
  wire             cpu_fpoint_s1_done_from_sa;
  wire    [  1: 0] cpu_fpoint_s1_n;
  wire             cpu_fpoint_s1_reset;
  wire    [ 31: 0] cpu_fpoint_s1_result;
  wire    [ 31: 0] cpu_fpoint_s1_result_from_sa;
  wire             cpu_fpoint_s1_select;
  wire             cpu_fpoint_s1_start;
  wire    [ 24: 0] cpu_instruction_master_address;
  wire    [ 24: 0] cpu_instruction_master_address_to_slave;
  wire    [  1: 0] cpu_instruction_master_dbs_address;
  wire             cpu_instruction_master_granted_cpu_jtag_debug_module;
  wire             cpu_instruction_master_granted_onchip_mem_s1;
  wire             cpu_instruction_master_latency_counter;
  wire             cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
  wire             cpu_instruction_master_qualified_request_onchip_mem_s1;
  wire             cpu_instruction_master_read;
  wire             cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
  wire             cpu_instruction_master_read_data_valid_onchip_mem_s1;
  wire    [ 31: 0] cpu_instruction_master_readdata;
  wire             cpu_instruction_master_readdatavalid;
  wire             cpu_instruction_master_requests_cpu_jtag_debug_module;
  wire             cpu_instruction_master_requests_onchip_mem_s1;
  wire             cpu_instruction_master_waitrequest;
  wire    [  8: 0] cpu_jtag_debug_module_address;
  wire             cpu_jtag_debug_module_begintransfer;
  wire    [  3: 0] cpu_jtag_debug_module_byteenable;
  wire             cpu_jtag_debug_module_chipselect;
  wire             cpu_jtag_debug_module_debugaccess;
  wire    [ 31: 0] cpu_jtag_debug_module_readdata;
  wire    [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
  wire             cpu_jtag_debug_module_reset;
  wire             cpu_jtag_debug_module_resetrequest;
  wire             cpu_jtag_debug_module_resetrequest_from_sa;
  wire             cpu_jtag_debug_module_write;
  wire    [ 31: 0] cpu_jtag_debug_module_writedata;
  wire             d1_AREA_s1_end_xfer;
  wire             d1_B1_s1_end_xfer;
  wire             d1_B2_s1_end_xfer;
  wire             d1_B3_s1_end_xfer;
  wire             d1_B4_s1_end_xfer;
  wire             d1_B5_s1_end_xfer;
  wire             d1_B6_s1_end_xfer;
  wire             d1_B7_s1_end_xfer;
  wire             d1_B8_s1_end_xfer;
  wire             d1_RESET_s1_end_xfer;
  wire             d1_XOFF_s1_end_xfer;
  wire             d1_YOFF_s1_end_xfer;
  wire             d1_cpu_jtag_debug_module_end_xfer;
  wire             d1_goIN_s1_end_xfer;
  wire             d1_goOUT_s1_end_xfer;
  wire             d1_jtag_uart_avalon_jtag_slave_end_xfer;
  wire             d1_onchip_mem_s1_end_xfer;
  wire    [  1: 0] goIN_s1_address;
  wire             goIN_s1_readdata;
  wire             goIN_s1_readdata_from_sa;
  wire             goIN_s1_reset_n;
  wire    [  1: 0] goOUT_s1_address;
  wire             goOUT_s1_chipselect;
  wire             goOUT_s1_reset_n;
  wire             goOUT_s1_write_n;
  wire             goOUT_s1_writedata;
  wire             jtag_uart_avalon_jtag_slave_address;
  wire             jtag_uart_avalon_jtag_slave_chipselect;
  wire             jtag_uart_avalon_jtag_slave_dataavailable;
  wire             jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
  wire             jtag_uart_avalon_jtag_slave_irq;
  wire             jtag_uart_avalon_jtag_slave_irq_from_sa;
  wire             jtag_uart_avalon_jtag_slave_read_n;
  wire    [ 31: 0] jtag_uart_avalon_jtag_slave_readdata;
  wire    [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
  wire             jtag_uart_avalon_jtag_slave_readyfordata;
  wire             jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
  wire             jtag_uart_avalon_jtag_slave_reset_n;
  wire             jtag_uart_avalon_jtag_slave_waitrequest;
  wire             jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
  wire             jtag_uart_avalon_jtag_slave_write_n;
  wire    [ 31: 0] jtag_uart_avalon_jtag_slave_writedata;
  wire    [ 12: 0] onchip_mem_s1_address;
  wire    [  1: 0] onchip_mem_s1_byteenable;
  wire             onchip_mem_s1_chipselect;
  wire             onchip_mem_s1_clken;
  wire    [ 15: 0] onchip_mem_s1_readdata;
  wire    [ 15: 0] onchip_mem_s1_readdata_from_sa;
  wire             onchip_mem_s1_write;
  wire    [ 15: 0] onchip_mem_s1_writedata;
  wire    [ 17: 0] out_port_from_the_B1;
  wire    [ 17: 0] out_port_from_the_B2;
  wire    [ 17: 0] out_port_from_the_B3;
  wire    [ 17: 0] out_port_from_the_B4;
  wire    [ 17: 0] out_port_from_the_B5;
  wire    [ 17: 0] out_port_from_the_B6;
  wire    [ 17: 0] out_port_from_the_B7;
  wire    [ 17: 0] out_port_from_the_B8;
  wire             out_port_from_the_goOUT;
  wire             registered_cpu_data_master_read_data_valid_onchip_mem_s1;
  wire             reset_n_sources;
  AREA_s1_arbitrator the_AREA_s1
    (
      .AREA_s1_address                           (AREA_s1_address),
      .AREA_s1_readdata                          (AREA_s1_readdata),
      .AREA_s1_readdata_from_sa                  (AREA_s1_readdata_from_sa),
      .AREA_s1_reset_n                           (AREA_s1_reset_n),
      .clk                                       (clk),
      .cpu_data_master_address_to_slave          (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_AREA_s1           (cpu_data_master_granted_AREA_s1),
      .cpu_data_master_qualified_request_AREA_s1 (cpu_data_master_qualified_request_AREA_s1),
      .cpu_data_master_read                      (cpu_data_master_read),
      .cpu_data_master_read_data_valid_AREA_s1   (cpu_data_master_read_data_valid_AREA_s1),
      .cpu_data_master_requests_AREA_s1          (cpu_data_master_requests_AREA_s1),
      .cpu_data_master_write                     (cpu_data_master_write),
      .d1_AREA_s1_end_xfer                       (d1_AREA_s1_end_xfer),
      .reset_n                                   (clk_reset_n)
    );

  AREA the_AREA
    (
      .address  (AREA_s1_address),
      .clk      (clk),
      .in_port  (in_port_to_the_AREA),
      .readdata (AREA_s1_readdata),
      .reset_n  (AREA_s1_reset_n)
    );

  B1_s1_arbitrator the_B1_s1
    (
      .B1_s1_address                           (B1_s1_address),
      .B1_s1_chipselect                        (B1_s1_chipselect),
      .B1_s1_reset_n                           (B1_s1_reset_n),
      .B1_s1_write_n                           (B1_s1_write_n),
      .B1_s1_writedata                         (B1_s1_writedata),
      .clk                                     (clk),
      .cpu_data_master_address_to_slave        (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_B1_s1           (cpu_data_master_granted_B1_s1),
      .cpu_data_master_qualified_request_B1_s1 (cpu_data_master_qualified_request_B1_s1),
      .cpu_data_master_read                    (cpu_data_master_read),
      .cpu_data_master_read_data_valid_B1_s1   (cpu_data_master_read_data_valid_B1_s1),
      .cpu_data_master_requests_B1_s1          (cpu_data_master_requests_B1_s1),
      .cpu_data_master_waitrequest             (cpu_data_master_waitrequest),
      .cpu_data_master_write                   (cpu_data_master_write),
      .cpu_data_master_writedata               (cpu_data_master_writedata),
      .d1_B1_s1_end_xfer                       (d1_B1_s1_end_xfer),
      .reset_n                                 (clk_reset_n)
    );

  B1 the_B1
    (
      .address    (B1_s1_address),
      .chipselect (B1_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_B1),
      .reset_n    (B1_s1_reset_n),
      .write_n    (B1_s1_write_n),
      .writedata  (B1_s1_writedata)
    );

  B2_s1_arbitrator the_B2_s1
    (
      .B2_s1_address                           (B2_s1_address),
      .B2_s1_chipselect                        (B2_s1_chipselect),
      .B2_s1_reset_n                           (B2_s1_reset_n),
      .B2_s1_write_n                           (B2_s1_write_n),
      .B2_s1_writedata                         (B2_s1_writedata),
      .clk                                     (clk),
      .cpu_data_master_address_to_slave        (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_B2_s1           (cpu_data_master_granted_B2_s1),
      .cpu_data_master_qualified_request_B2_s1 (cpu_data_master_qualified_request_B2_s1),
      .cpu_data_master_read                    (cpu_data_master_read),
      .cpu_data_master_read_data_valid_B2_s1   (cpu_data_master_read_data_valid_B2_s1),
      .cpu_data_master_requests_B2_s1          (cpu_data_master_requests_B2_s1),
      .cpu_data_master_waitrequest             (cpu_data_master_waitrequest),
      .cpu_data_master_write                   (cpu_data_master_write),
      .cpu_data_master_writedata               (cpu_data_master_writedata),
      .d1_B2_s1_end_xfer                       (d1_B2_s1_end_xfer),
      .reset_n                                 (clk_reset_n)
    );

  B2 the_B2
    (
      .address    (B2_s1_address),
      .chipselect (B2_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_B2),
      .reset_n    (B2_s1_reset_n),
      .write_n    (B2_s1_write_n),
      .writedata  (B2_s1_writedata)
    );

  B3_s1_arbitrator the_B3_s1
    (
      .B3_s1_address                           (B3_s1_address),
      .B3_s1_chipselect                        (B3_s1_chipselect),
      .B3_s1_reset_n                           (B3_s1_reset_n),
      .B3_s1_write_n                           (B3_s1_write_n),
      .B3_s1_writedata                         (B3_s1_writedata),
      .clk                                     (clk),
      .cpu_data_master_address_to_slave        (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_B3_s1           (cpu_data_master_granted_B3_s1),
      .cpu_data_master_qualified_request_B3_s1 (cpu_data_master_qualified_request_B3_s1),
      .cpu_data_master_read                    (cpu_data_master_read),
      .cpu_data_master_read_data_valid_B3_s1   (cpu_data_master_read_data_valid_B3_s1),
      .cpu_data_master_requests_B3_s1          (cpu_data_master_requests_B3_s1),
      .cpu_data_master_waitrequest             (cpu_data_master_waitrequest),
      .cpu_data_master_write                   (cpu_data_master_write),
      .cpu_data_master_writedata               (cpu_data_master_writedata),
      .d1_B3_s1_end_xfer                       (d1_B3_s1_end_xfer),
      .reset_n                                 (clk_reset_n)
    );

  B3 the_B3
    (
      .address    (B3_s1_address),
      .chipselect (B3_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_B3),
      .reset_n    (B3_s1_reset_n),
      .write_n    (B3_s1_write_n),
      .writedata  (B3_s1_writedata)
    );

  B4_s1_arbitrator the_B4_s1
    (
      .B4_s1_address                           (B4_s1_address),
      .B4_s1_chipselect                        (B4_s1_chipselect),
      .B4_s1_reset_n                           (B4_s1_reset_n),
      .B4_s1_write_n                           (B4_s1_write_n),
      .B4_s1_writedata                         (B4_s1_writedata),
      .clk                                     (clk),
      .cpu_data_master_address_to_slave        (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_B4_s1           (cpu_data_master_granted_B4_s1),
      .cpu_data_master_qualified_request_B4_s1 (cpu_data_master_qualified_request_B4_s1),
      .cpu_data_master_read                    (cpu_data_master_read),
      .cpu_data_master_read_data_valid_B4_s1   (cpu_data_master_read_data_valid_B4_s1),
      .cpu_data_master_requests_B4_s1          (cpu_data_master_requests_B4_s1),
      .cpu_data_master_waitrequest             (cpu_data_master_waitrequest),
      .cpu_data_master_write                   (cpu_data_master_write),
      .cpu_data_master_writedata               (cpu_data_master_writedata),
      .d1_B4_s1_end_xfer                       (d1_B4_s1_end_xfer),
      .reset_n                                 (clk_reset_n)
    );

  B4 the_B4
    (
      .address    (B4_s1_address),
      .chipselect (B4_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_B4),
      .reset_n    (B4_s1_reset_n),
      .write_n    (B4_s1_write_n),
      .writedata  (B4_s1_writedata)
    );

  B5_s1_arbitrator the_B5_s1
    (
      .B5_s1_address                           (B5_s1_address),
      .B5_s1_chipselect                        (B5_s1_chipselect),
      .B5_s1_reset_n                           (B5_s1_reset_n),
      .B5_s1_write_n                           (B5_s1_write_n),
      .B5_s1_writedata                         (B5_s1_writedata),
      .clk                                     (clk),
      .cpu_data_master_address_to_slave        (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_B5_s1           (cpu_data_master_granted_B5_s1),
      .cpu_data_master_qualified_request_B5_s1 (cpu_data_master_qualified_request_B5_s1),
      .cpu_data_master_read                    (cpu_data_master_read),
      .cpu_data_master_read_data_valid_B5_s1   (cpu_data_master_read_data_valid_B5_s1),
      .cpu_data_master_requests_B5_s1          (cpu_data_master_requests_B5_s1),
      .cpu_data_master_waitrequest             (cpu_data_master_waitrequest),
      .cpu_data_master_write                   (cpu_data_master_write),
      .cpu_data_master_writedata               (cpu_data_master_writedata),
      .d1_B5_s1_end_xfer                       (d1_B5_s1_end_xfer),
      .reset_n                                 (clk_reset_n)
    );

  B5 the_B5
    (
      .address    (B5_s1_address),
      .chipselect (B5_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_B5),
      .reset_n    (B5_s1_reset_n),
      .write_n    (B5_s1_write_n),
      .writedata  (B5_s1_writedata)
    );

  B6_s1_arbitrator the_B6_s1
    (
      .B6_s1_address                           (B6_s1_address),
      .B6_s1_chipselect                        (B6_s1_chipselect),
      .B6_s1_reset_n                           (B6_s1_reset_n),
      .B6_s1_write_n                           (B6_s1_write_n),
      .B6_s1_writedata                         (B6_s1_writedata),
      .clk                                     (clk),
      .cpu_data_master_address_to_slave        (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_B6_s1           (cpu_data_master_granted_B6_s1),
      .cpu_data_master_qualified_request_B6_s1 (cpu_data_master_qualified_request_B6_s1),
      .cpu_data_master_read                    (cpu_data_master_read),
      .cpu_data_master_read_data_valid_B6_s1   (cpu_data_master_read_data_valid_B6_s1),
      .cpu_data_master_requests_B6_s1          (cpu_data_master_requests_B6_s1),
      .cpu_data_master_waitrequest             (cpu_data_master_waitrequest),
      .cpu_data_master_write                   (cpu_data_master_write),
      .cpu_data_master_writedata               (cpu_data_master_writedata),
      .d1_B6_s1_end_xfer                       (d1_B6_s1_end_xfer),
      .reset_n                                 (clk_reset_n)
    );

  B6 the_B6
    (
      .address    (B6_s1_address),
      .chipselect (B6_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_B6),
      .reset_n    (B6_s1_reset_n),
      .write_n    (B6_s1_write_n),
      .writedata  (B6_s1_writedata)
    );

  B7_s1_arbitrator the_B7_s1
    (
      .B7_s1_address                           (B7_s1_address),
      .B7_s1_chipselect                        (B7_s1_chipselect),
      .B7_s1_reset_n                           (B7_s1_reset_n),
      .B7_s1_write_n                           (B7_s1_write_n),
      .B7_s1_writedata                         (B7_s1_writedata),
      .clk                                     (clk),
      .cpu_data_master_address_to_slave        (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_B7_s1           (cpu_data_master_granted_B7_s1),
      .cpu_data_master_qualified_request_B7_s1 (cpu_data_master_qualified_request_B7_s1),
      .cpu_data_master_read                    (cpu_data_master_read),
      .cpu_data_master_read_data_valid_B7_s1   (cpu_data_master_read_data_valid_B7_s1),
      .cpu_data_master_requests_B7_s1          (cpu_data_master_requests_B7_s1),
      .cpu_data_master_waitrequest             (cpu_data_master_waitrequest),
      .cpu_data_master_write                   (cpu_data_master_write),
      .cpu_data_master_writedata               (cpu_data_master_writedata),
      .d1_B7_s1_end_xfer                       (d1_B7_s1_end_xfer),
      .reset_n                                 (clk_reset_n)
    );

  B7 the_B7
    (
      .address    (B7_s1_address),
      .chipselect (B7_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_B7),
      .reset_n    (B7_s1_reset_n),
      .write_n    (B7_s1_write_n),
      .writedata  (B7_s1_writedata)
    );

  B8_s1_arbitrator the_B8_s1
    (
      .B8_s1_address                           (B8_s1_address),
      .B8_s1_chipselect                        (B8_s1_chipselect),
      .B8_s1_reset_n                           (B8_s1_reset_n),
      .B8_s1_write_n                           (B8_s1_write_n),
      .B8_s1_writedata                         (B8_s1_writedata),
      .clk                                     (clk),
      .cpu_data_master_address_to_slave        (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_B8_s1           (cpu_data_master_granted_B8_s1),
      .cpu_data_master_qualified_request_B8_s1 (cpu_data_master_qualified_request_B8_s1),
      .cpu_data_master_read                    (cpu_data_master_read),
      .cpu_data_master_read_data_valid_B8_s1   (cpu_data_master_read_data_valid_B8_s1),
      .cpu_data_master_requests_B8_s1          (cpu_data_master_requests_B8_s1),
      .cpu_data_master_waitrequest             (cpu_data_master_waitrequest),
      .cpu_data_master_write                   (cpu_data_master_write),
      .cpu_data_master_writedata               (cpu_data_master_writedata),
      .d1_B8_s1_end_xfer                       (d1_B8_s1_end_xfer),
      .reset_n                                 (clk_reset_n)
    );

  B8 the_B8
    (
      .address    (B8_s1_address),
      .chipselect (B8_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_B8),
      .reset_n    (B8_s1_reset_n),
      .write_n    (B8_s1_write_n),
      .writedata  (B8_s1_writedata)
    );

  RESET_s1_arbitrator the_RESET_s1
    (
      .RESET_s1_address                           (RESET_s1_address),
      .RESET_s1_readdata                          (RESET_s1_readdata),
      .RESET_s1_readdata_from_sa                  (RESET_s1_readdata_from_sa),
      .RESET_s1_reset_n                           (RESET_s1_reset_n),
      .clk                                        (clk),
      .cpu_data_master_address_to_slave           (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_RESET_s1           (cpu_data_master_granted_RESET_s1),
      .cpu_data_master_qualified_request_RESET_s1 (cpu_data_master_qualified_request_RESET_s1),
      .cpu_data_master_read                       (cpu_data_master_read),
      .cpu_data_master_read_data_valid_RESET_s1   (cpu_data_master_read_data_valid_RESET_s1),
      .cpu_data_master_requests_RESET_s1          (cpu_data_master_requests_RESET_s1),
      .cpu_data_master_write                      (cpu_data_master_write),
      .d1_RESET_s1_end_xfer                       (d1_RESET_s1_end_xfer),
      .reset_n                                    (clk_reset_n)
    );

  RESET the_RESET
    (
      .address  (RESET_s1_address),
      .clk      (clk),
      .in_port  (in_port_to_the_RESET),
      .readdata (RESET_s1_readdata),
      .reset_n  (RESET_s1_reset_n)
    );

  XOFF_s1_arbitrator the_XOFF_s1
    (
      .XOFF_s1_address                           (XOFF_s1_address),
      .XOFF_s1_readdata                          (XOFF_s1_readdata),
      .XOFF_s1_readdata_from_sa                  (XOFF_s1_readdata_from_sa),
      .XOFF_s1_reset_n                           (XOFF_s1_reset_n),
      .clk                                       (clk),
      .cpu_data_master_address_to_slave          (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_XOFF_s1           (cpu_data_master_granted_XOFF_s1),
      .cpu_data_master_qualified_request_XOFF_s1 (cpu_data_master_qualified_request_XOFF_s1),
      .cpu_data_master_read                      (cpu_data_master_read),
      .cpu_data_master_read_data_valid_XOFF_s1   (cpu_data_master_read_data_valid_XOFF_s1),
      .cpu_data_master_requests_XOFF_s1          (cpu_data_master_requests_XOFF_s1),
      .cpu_data_master_write                     (cpu_data_master_write),
      .d1_XOFF_s1_end_xfer                       (d1_XOFF_s1_end_xfer),
      .reset_n                                   (clk_reset_n)
    );

  XOFF the_XOFF
    (
      .address  (XOFF_s1_address),
      .clk      (clk),
      .in_port  (in_port_to_the_XOFF),
      .readdata (XOFF_s1_readdata),
      .reset_n  (XOFF_s1_reset_n)
    );

  YOFF_s1_arbitrator the_YOFF_s1
    (
      .YOFF_s1_address                           (YOFF_s1_address),
      .YOFF_s1_readdata                          (YOFF_s1_readdata),
      .YOFF_s1_readdata_from_sa                  (YOFF_s1_readdata_from_sa),
      .YOFF_s1_reset_n                           (YOFF_s1_reset_n),
      .clk                                       (clk),
      .cpu_data_master_address_to_slave          (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_YOFF_s1           (cpu_data_master_granted_YOFF_s1),
      .cpu_data_master_qualified_request_YOFF_s1 (cpu_data_master_qualified_request_YOFF_s1),
      .cpu_data_master_read                      (cpu_data_master_read),
      .cpu_data_master_read_data_valid_YOFF_s1   (cpu_data_master_read_data_valid_YOFF_s1),
      .cpu_data_master_requests_YOFF_s1          (cpu_data_master_requests_YOFF_s1),
      .cpu_data_master_write                     (cpu_data_master_write),
      .d1_YOFF_s1_end_xfer                       (d1_YOFF_s1_end_xfer),
      .reset_n                                   (clk_reset_n)
    );

  YOFF the_YOFF
    (
      .address  (YOFF_s1_address),
      .clk      (clk),
      .in_port  (in_port_to_the_YOFF),
      .readdata (YOFF_s1_readdata),
      .reset_n  (YOFF_s1_reset_n)
    );

  cpu_jtag_debug_module_arbitrator the_cpu_jtag_debug_module
    (
      .clk                                                            (clk),
      .cpu_data_master_address_to_slave                               (cpu_data_master_address_to_slave),
      .cpu_data_master_byteenable                                     (cpu_data_master_byteenable),
      .cpu_data_master_debugaccess                                    (cpu_data_master_debugaccess),
      .cpu_data_master_granted_cpu_jtag_debug_module                  (cpu_data_master_granted_cpu_jtag_debug_module),
      .cpu_data_master_qualified_request_cpu_jtag_debug_module        (cpu_data_master_qualified_request_cpu_jtag_debug_module),
      .cpu_data_master_read                                           (cpu_data_master_read),
      .cpu_data_master_read_data_valid_cpu_jtag_debug_module          (cpu_data_master_read_data_valid_cpu_jtag_debug_module),
      .cpu_data_master_requests_cpu_jtag_debug_module                 (cpu_data_master_requests_cpu_jtag_debug_module),
      .cpu_data_master_waitrequest                                    (cpu_data_master_waitrequest),
      .cpu_data_master_write                                          (cpu_data_master_write),
      .cpu_data_master_writedata                                      (cpu_data_master_writedata),
      .cpu_instruction_master_address_to_slave                        (cpu_instruction_master_address_to_slave),
      .cpu_instruction_master_granted_cpu_jtag_debug_module           (cpu_instruction_master_granted_cpu_jtag_debug_module),
      .cpu_instruction_master_latency_counter                         (cpu_instruction_master_latency_counter),
      .cpu_instruction_master_qualified_request_cpu_jtag_debug_module (cpu_instruction_master_qualified_request_cpu_jtag_debug_module),
      .cpu_instruction_master_read                                    (cpu_instruction_master_read),
      .cpu_instruction_master_read_data_valid_cpu_jtag_debug_module   (cpu_instruction_master_read_data_valid_cpu_jtag_debug_module),
      .cpu_instruction_master_requests_cpu_jtag_debug_module          (cpu_instruction_master_requests_cpu_jtag_debug_module),
      .cpu_jtag_debug_module_address                                  (cpu_jtag_debug_module_address),
      .cpu_jtag_debug_module_begintransfer                            (cpu_jtag_debug_module_begintransfer),
      .cpu_jtag_debug_module_byteenable                               (cpu_jtag_debug_module_byteenable),
      .cpu_jtag_debug_module_chipselect                               (cpu_jtag_debug_module_chipselect),
      .cpu_jtag_debug_module_debugaccess                              (cpu_jtag_debug_module_debugaccess),
      .cpu_jtag_debug_module_readdata                                 (cpu_jtag_debug_module_readdata),
      .cpu_jtag_debug_module_readdata_from_sa                         (cpu_jtag_debug_module_readdata_from_sa),
      .cpu_jtag_debug_module_reset                                    (cpu_jtag_debug_module_reset),
      .cpu_jtag_debug_module_resetrequest                             (cpu_jtag_debug_module_resetrequest),
      .cpu_jtag_debug_module_resetrequest_from_sa                     (cpu_jtag_debug_module_resetrequest_from_sa),
      .cpu_jtag_debug_module_write                                    (cpu_jtag_debug_module_write),
      .cpu_jtag_debug_module_writedata                                (cpu_jtag_debug_module_writedata),
      .d1_cpu_jtag_debug_module_end_xfer                              (d1_cpu_jtag_debug_module_end_xfer),
      .reset_n                                                        (clk_reset_n)
    );

  cpu_custom_instruction_master_arbitrator the_cpu_custom_instruction_master
    (
      .clk                                               (clk),
      .cpu_custom_instruction_master_multi_done          (cpu_custom_instruction_master_multi_done),
      .cpu_custom_instruction_master_multi_result        (cpu_custom_instruction_master_multi_result),
      .cpu_custom_instruction_master_multi_start         (cpu_custom_instruction_master_multi_start),
      .cpu_custom_instruction_master_reset_n             (cpu_custom_instruction_master_reset_n),
      .cpu_custom_instruction_master_start_cpu_fpoint_s1 (cpu_custom_instruction_master_start_cpu_fpoint_s1),
      .cpu_fpoint_s1_done_from_sa                        (cpu_fpoint_s1_done_from_sa),
      .cpu_fpoint_s1_result_from_sa                      (cpu_fpoint_s1_result_from_sa),
      .cpu_fpoint_s1_select                              (cpu_fpoint_s1_select),
      .reset_n                                           (clk_reset_n)
    );

  cpu_data_master_arbitrator the_cpu_data_master
    (
      .AREA_s1_readdata_from_sa                                      (AREA_s1_readdata_from_sa),
      .RESET_s1_readdata_from_sa                                     (RESET_s1_readdata_from_sa),
      .XOFF_s1_readdata_from_sa                                      (XOFF_s1_readdata_from_sa),
      .YOFF_s1_readdata_from_sa                                      (YOFF_s1_readdata_from_sa),
      .clk                                                           (clk),
      .cpu_data_master_address                                       (cpu_data_master_address),
      .cpu_data_master_address_to_slave                              (cpu_data_master_address_to_slave),
      .cpu_data_master_byteenable_onchip_mem_s1                      (cpu_data_master_byteenable_onchip_mem_s1),
      .cpu_data_master_dbs_address                                   (cpu_data_master_dbs_address),
      .cpu_data_master_dbs_write_16                                  (cpu_data_master_dbs_write_16),
      .cpu_data_master_granted_AREA_s1                               (cpu_data_master_granted_AREA_s1),
      .cpu_data_master_granted_B1_s1                                 (cpu_data_master_granted_B1_s1),
      .cpu_data_master_granted_B2_s1                                 (cpu_data_master_granted_B2_s1),
      .cpu_data_master_granted_B3_s1                                 (cpu_data_master_granted_B3_s1),
      .cpu_data_master_granted_B4_s1                                 (cpu_data_master_granted_B4_s1),
      .cpu_data_master_granted_B5_s1                                 (cpu_data_master_granted_B5_s1),
      .cpu_data_master_granted_B6_s1                                 (cpu_data_master_granted_B6_s1),
      .cpu_data_master_granted_B7_s1                                 (cpu_data_master_granted_B7_s1),
      .cpu_data_master_granted_B8_s1                                 (cpu_data_master_granted_B8_s1),
      .cpu_data_master_granted_RESET_s1                              (cpu_data_master_granted_RESET_s1),
      .cpu_data_master_granted_XOFF_s1                               (cpu_data_master_granted_XOFF_s1),
      .cpu_data_master_granted_YOFF_s1                               (cpu_data_master_granted_YOFF_s1),
      .cpu_data_master_granted_cpu_jtag_debug_module                 (cpu_data_master_granted_cpu_jtag_debug_module),
      .cpu_data_master_granted_goIN_s1                               (cpu_data_master_granted_goIN_s1),
      .cpu_data_master_granted_goOUT_s1                              (cpu_data_master_granted_goOUT_s1),
      .cpu_data_master_granted_jtag_uart_avalon_jtag_slave           (cpu_data_master_granted_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_granted_onchip_mem_s1                         (cpu_data_master_granted_onchip_mem_s1),
      .cpu_data_master_irq                                           (cpu_data_master_irq),
      .cpu_data_master_no_byte_enables_and_last_term                 (cpu_data_master_no_byte_enables_and_last_term),
      .cpu_data_master_qualified_request_AREA_s1                     (cpu_data_master_qualified_request_AREA_s1),
      .cpu_data_master_qualified_request_B1_s1                       (cpu_data_master_qualified_request_B1_s1),
      .cpu_data_master_qualified_request_B2_s1                       (cpu_data_master_qualified_request_B2_s1),
      .cpu_data_master_qualified_request_B3_s1                       (cpu_data_master_qualified_request_B3_s1),
      .cpu_data_master_qualified_request_B4_s1                       (cpu_data_master_qualified_request_B4_s1),
      .cpu_data_master_qualified_request_B5_s1                       (cpu_data_master_qualified_request_B5_s1),
      .cpu_data_master_qualified_request_B6_s1                       (cpu_data_master_qualified_request_B6_s1),
      .cpu_data_master_qualified_request_B7_s1                       (cpu_data_master_qualified_request_B7_s1),
      .cpu_data_master_qualified_request_B8_s1                       (cpu_data_master_qualified_request_B8_s1),
      .cpu_data_master_qualified_request_RESET_s1                    (cpu_data_master_qualified_request_RESET_s1),
      .cpu_data_master_qualified_request_XOFF_s1                     (cpu_data_master_qualified_request_XOFF_s1),
      .cpu_data_master_qualified_request_YOFF_s1                     (cpu_data_master_qualified_request_YOFF_s1),
      .cpu_data_master_qualified_request_cpu_jtag_debug_module       (cpu_data_master_qualified_request_cpu_jtag_debug_module),
      .cpu_data_master_qualified_request_goIN_s1                     (cpu_data_master_qualified_request_goIN_s1),
      .cpu_data_master_qualified_request_goOUT_s1                    (cpu_data_master_qualified_request_goOUT_s1),
      .cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave (cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_qualified_request_onchip_mem_s1               (cpu_data_master_qualified_request_onchip_mem_s1),
      .cpu_data_master_read                                          (cpu_data_master_read),
      .cpu_data_master_read_data_valid_AREA_s1                       (cpu_data_master_read_data_valid_AREA_s1),
      .cpu_data_master_read_data_valid_B1_s1                         (cpu_data_master_read_data_valid_B1_s1),
      .cpu_data_master_read_data_valid_B2_s1                         (cpu_data_master_read_data_valid_B2_s1),
      .cpu_data_master_read_data_valid_B3_s1                         (cpu_data_master_read_data_valid_B3_s1),
      .cpu_data_master_read_data_valid_B4_s1                         (cpu_data_master_read_data_valid_B4_s1),
      .cpu_data_master_read_data_valid_B5_s1                         (cpu_data_master_read_data_valid_B5_s1),
      .cpu_data_master_read_data_valid_B6_s1                         (cpu_data_master_read_data_valid_B6_s1),
      .cpu_data_master_read_data_valid_B7_s1                         (cpu_data_master_read_data_valid_B7_s1),
      .cpu_data_master_read_data_valid_B8_s1                         (cpu_data_master_read_data_valid_B8_s1),
      .cpu_data_master_read_data_valid_RESET_s1                      (cpu_data_master_read_data_valid_RESET_s1),
      .cpu_data_master_read_data_valid_XOFF_s1                       (cpu_data_master_read_data_valid_XOFF_s1),
      .cpu_data_master_read_data_valid_YOFF_s1                       (cpu_data_master_read_data_valid_YOFF_s1),
      .cpu_data_master_read_data_valid_cpu_jtag_debug_module         (cpu_data_master_read_data_valid_cpu_jtag_debug_module),
      .cpu_data_master_read_data_valid_goIN_s1                       (cpu_data_master_read_data_valid_goIN_s1),
      .cpu_data_master_read_data_valid_goOUT_s1                      (cpu_data_master_read_data_valid_goOUT_s1),
      .cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave   (cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_read_data_valid_onchip_mem_s1                 (cpu_data_master_read_data_valid_onchip_mem_s1),
      .cpu_data_master_readdata                                      (cpu_data_master_readdata),
      .cpu_data_master_requests_AREA_s1                              (cpu_data_master_requests_AREA_s1),
      .cpu_data_master_requests_B1_s1                                (cpu_data_master_requests_B1_s1),
      .cpu_data_master_requests_B2_s1                                (cpu_data_master_requests_B2_s1),
      .cpu_data_master_requests_B3_s1                                (cpu_data_master_requests_B3_s1),
      .cpu_data_master_requests_B4_s1                                (cpu_data_master_requests_B4_s1),
      .cpu_data_master_requests_B5_s1                                (cpu_data_master_requests_B5_s1),
      .cpu_data_master_requests_B6_s1                                (cpu_data_master_requests_B6_s1),
      .cpu_data_master_requests_B7_s1                                (cpu_data_master_requests_B7_s1),
      .cpu_data_master_requests_B8_s1                                (cpu_data_master_requests_B8_s1),
      .cpu_data_master_requests_RESET_s1                             (cpu_data_master_requests_RESET_s1),
      .cpu_data_master_requests_XOFF_s1                              (cpu_data_master_requests_XOFF_s1),
      .cpu_data_master_requests_YOFF_s1                              (cpu_data_master_requests_YOFF_s1),
      .cpu_data_master_requests_cpu_jtag_debug_module                (cpu_data_master_requests_cpu_jtag_debug_module),
      .cpu_data_master_requests_goIN_s1                              (cpu_data_master_requests_goIN_s1),
      .cpu_data_master_requests_goOUT_s1                             (cpu_data_master_requests_goOUT_s1),
      .cpu_data_master_requests_jtag_uart_avalon_jtag_slave          (cpu_data_master_requests_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_requests_onchip_mem_s1                        (cpu_data_master_requests_onchip_mem_s1),
      .cpu_data_master_waitrequest                                   (cpu_data_master_waitrequest),
      .cpu_data_master_write                                         (cpu_data_master_write),
      .cpu_data_master_writedata                                     (cpu_data_master_writedata),
      .cpu_jtag_debug_module_readdata_from_sa                        (cpu_jtag_debug_module_readdata_from_sa),
      .d1_AREA_s1_end_xfer                                           (d1_AREA_s1_end_xfer),
      .d1_B1_s1_end_xfer                                             (d1_B1_s1_end_xfer),
      .d1_B2_s1_end_xfer                                             (d1_B2_s1_end_xfer),
      .d1_B3_s1_end_xfer                                             (d1_B3_s1_end_xfer),
      .d1_B4_s1_end_xfer                                             (d1_B4_s1_end_xfer),
      .d1_B5_s1_end_xfer                                             (d1_B5_s1_end_xfer),
      .d1_B6_s1_end_xfer                                             (d1_B6_s1_end_xfer),
      .d1_B7_s1_end_xfer                                             (d1_B7_s1_end_xfer),
      .d1_B8_s1_end_xfer                                             (d1_B8_s1_end_xfer),
      .d1_RESET_s1_end_xfer                                          (d1_RESET_s1_end_xfer),
      .d1_XOFF_s1_end_xfer                                           (d1_XOFF_s1_end_xfer),
      .d1_YOFF_s1_end_xfer                                           (d1_YOFF_s1_end_xfer),
      .d1_cpu_jtag_debug_module_end_xfer                             (d1_cpu_jtag_debug_module_end_xfer),
      .d1_goIN_s1_end_xfer                                           (d1_goIN_s1_end_xfer),
      .d1_goOUT_s1_end_xfer                                          (d1_goOUT_s1_end_xfer),
      .d1_jtag_uart_avalon_jtag_slave_end_xfer                       (d1_jtag_uart_avalon_jtag_slave_end_xfer),
      .d1_onchip_mem_s1_end_xfer                                     (d1_onchip_mem_s1_end_xfer),
      .goIN_s1_readdata_from_sa                                      (goIN_s1_readdata_from_sa),
      .jtag_uart_avalon_jtag_slave_irq_from_sa                       (jtag_uart_avalon_jtag_slave_irq_from_sa),
      .jtag_uart_avalon_jtag_slave_readdata_from_sa                  (jtag_uart_avalon_jtag_slave_readdata_from_sa),
      .jtag_uart_avalon_jtag_slave_waitrequest_from_sa               (jtag_uart_avalon_jtag_slave_waitrequest_from_sa),
      .onchip_mem_s1_readdata_from_sa                                (onchip_mem_s1_readdata_from_sa),
      .registered_cpu_data_master_read_data_valid_onchip_mem_s1      (registered_cpu_data_master_read_data_valid_onchip_mem_s1),
      .reset_n                                                       (clk_reset_n)
    );

  cpu_instruction_master_arbitrator the_cpu_instruction_master
    (
      .clk                                                            (clk),
      .cpu_instruction_master_address                                 (cpu_instruction_master_address),
      .cpu_instruction_master_address_to_slave                        (cpu_instruction_master_address_to_slave),
      .cpu_instruction_master_dbs_address                             (cpu_instruction_master_dbs_address),
      .cpu_instruction_master_granted_cpu_jtag_debug_module           (cpu_instruction_master_granted_cpu_jtag_debug_module),
      .cpu_instruction_master_granted_onchip_mem_s1                   (cpu_instruction_master_granted_onchip_mem_s1),
      .cpu_instruction_master_latency_counter                         (cpu_instruction_master_latency_counter),
      .cpu_instruction_master_qualified_request_cpu_jtag_debug_module (cpu_instruction_master_qualified_request_cpu_jtag_debug_module),
      .cpu_instruction_master_qualified_request_onchip_mem_s1         (cpu_instruction_master_qualified_request_onchip_mem_s1),
      .cpu_instruction_master_read                                    (cpu_instruction_master_read),
      .cpu_instruction_master_read_data_valid_cpu_jtag_debug_module   (cpu_instruction_master_read_data_valid_cpu_jtag_debug_module),
      .cpu_instruction_master_read_data_valid_onchip_mem_s1           (cpu_instruction_master_read_data_valid_onchip_mem_s1),
      .cpu_instruction_master_readdata                                (cpu_instruction_master_readdata),
      .cpu_instruction_master_readdatavalid                           (cpu_instruction_master_readdatavalid),
      .cpu_instruction_master_requests_cpu_jtag_debug_module          (cpu_instruction_master_requests_cpu_jtag_debug_module),
      .cpu_instruction_master_requests_onchip_mem_s1                  (cpu_instruction_master_requests_onchip_mem_s1),
      .cpu_instruction_master_waitrequest                             (cpu_instruction_master_waitrequest),
      .cpu_jtag_debug_module_readdata_from_sa                         (cpu_jtag_debug_module_readdata_from_sa),
      .d1_cpu_jtag_debug_module_end_xfer                              (d1_cpu_jtag_debug_module_end_xfer),
      .d1_onchip_mem_s1_end_xfer                                      (d1_onchip_mem_s1_end_xfer),
      .onchip_mem_s1_readdata_from_sa                                 (onchip_mem_s1_readdata_from_sa),
      .reset_n                                                        (clk_reset_n)
    );

  cpu the_cpu
    (
      .M_ci_multi_a                          (cpu_custom_instruction_master_multi_a),
      .M_ci_multi_b                          (cpu_custom_instruction_master_multi_b),
      .M_ci_multi_c                          (cpu_custom_instruction_master_multi_c),
      .M_ci_multi_clk_en                     (cpu_custom_instruction_master_multi_clk_en),
      .M_ci_multi_dataa                      (cpu_custom_instruction_master_multi_dataa),
      .M_ci_multi_datab                      (cpu_custom_instruction_master_multi_datab),
      .M_ci_multi_done                       (cpu_custom_instruction_master_multi_done),
      .M_ci_multi_estatus                    (cpu_custom_instruction_master_multi_estatus),
      .M_ci_multi_ipending                   (cpu_custom_instruction_master_multi_ipending),
      .M_ci_multi_n                          (cpu_custom_instruction_master_multi_n),
      .M_ci_multi_readra                     (cpu_custom_instruction_master_multi_readra),
      .M_ci_multi_readrb                     (cpu_custom_instruction_master_multi_readrb),
      .M_ci_multi_result                     (cpu_custom_instruction_master_multi_result),
      .M_ci_multi_start                      (cpu_custom_instruction_master_multi_start),
      .M_ci_multi_status                     (cpu_custom_instruction_master_multi_status),
      .M_ci_multi_writerc                    (cpu_custom_instruction_master_multi_writerc),
      .clk                                   (clk),
      .d_address                             (cpu_data_master_address),
      .d_byteenable                          (cpu_data_master_byteenable),
      .d_irq                                 (cpu_data_master_irq),
      .d_read                                (cpu_data_master_read),
      .d_readdata                            (cpu_data_master_readdata),
      .d_waitrequest                         (cpu_data_master_waitrequest),
      .d_write                               (cpu_data_master_write),
      .d_writedata                           (cpu_data_master_writedata),
      .i_address                             (cpu_instruction_master_address),
      .i_read                                (cpu_instruction_master_read),
      .i_readdata                            (cpu_instruction_master_readdata),
      .i_readdatavalid                       (cpu_instruction_master_readdatavalid),
      .i_waitrequest                         (cpu_instruction_master_waitrequest),
      .jtag_debug_module_address             (cpu_jtag_debug_module_address),
      .jtag_debug_module_begintransfer       (cpu_jtag_debug_module_begintransfer),
      .jtag_debug_module_byteenable          (cpu_jtag_debug_module_byteenable),
      .jtag_debug_module_clk                 (clk),
      .jtag_debug_module_debugaccess         (cpu_jtag_debug_module_debugaccess),
      .jtag_debug_module_debugaccess_to_roms (cpu_data_master_debugaccess),
      .jtag_debug_module_readdata            (cpu_jtag_debug_module_readdata),
      .jtag_debug_module_reset               (cpu_jtag_debug_module_reset),
      .jtag_debug_module_resetrequest        (cpu_jtag_debug_module_resetrequest),
      .jtag_debug_module_select              (cpu_jtag_debug_module_chipselect),
      .jtag_debug_module_write               (cpu_jtag_debug_module_write),
      .jtag_debug_module_writedata           (cpu_jtag_debug_module_writedata),
      .reset_n                               (cpu_custom_instruction_master_reset_n)
    );

  cpu_fpoint_s1_arbitrator the_cpu_fpoint_s1
    (
      .clk                                               (clk),
      .cpu_custom_instruction_master_multi_clk_en        (cpu_custom_instruction_master_multi_clk_en),
      .cpu_custom_instruction_master_multi_dataa         (cpu_custom_instruction_master_multi_dataa),
      .cpu_custom_instruction_master_multi_datab         (cpu_custom_instruction_master_multi_datab),
      .cpu_custom_instruction_master_multi_n             (cpu_custom_instruction_master_multi_n),
      .cpu_custom_instruction_master_start_cpu_fpoint_s1 (cpu_custom_instruction_master_start_cpu_fpoint_s1),
      .cpu_fpoint_s1_clk_en                              (cpu_fpoint_s1_clk_en),
      .cpu_fpoint_s1_dataa                               (cpu_fpoint_s1_dataa),
      .cpu_fpoint_s1_datab                               (cpu_fpoint_s1_datab),
      .cpu_fpoint_s1_done                                (cpu_fpoint_s1_done),
      .cpu_fpoint_s1_done_from_sa                        (cpu_fpoint_s1_done_from_sa),
      .cpu_fpoint_s1_n                                   (cpu_fpoint_s1_n),
      .cpu_fpoint_s1_reset                               (cpu_fpoint_s1_reset),
      .cpu_fpoint_s1_result                              (cpu_fpoint_s1_result),
      .cpu_fpoint_s1_result_from_sa                      (cpu_fpoint_s1_result_from_sa),
      .cpu_fpoint_s1_select                              (cpu_fpoint_s1_select),
      .cpu_fpoint_s1_start                               (cpu_fpoint_s1_start),
      .reset_n                                           (clk_reset_n)
    );

  cpu_fpoint the_cpu_fpoint
    (
      .clk    (clk),
      .clk_en (cpu_fpoint_s1_clk_en),
      .dataa  (cpu_fpoint_s1_dataa),
      .datab  (cpu_fpoint_s1_datab),
      .done   (cpu_fpoint_s1_done),
      .n      (cpu_fpoint_s1_n),
      .reset  (cpu_fpoint_s1_reset),
      .result (cpu_fpoint_s1_result),
      .start  (cpu_fpoint_s1_start)
    );

  goIN_s1_arbitrator the_goIN_s1
    (
      .clk                                       (clk),
      .cpu_data_master_address_to_slave          (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_goIN_s1           (cpu_data_master_granted_goIN_s1),
      .cpu_data_master_qualified_request_goIN_s1 (cpu_data_master_qualified_request_goIN_s1),
      .cpu_data_master_read                      (cpu_data_master_read),
      .cpu_data_master_read_data_valid_goIN_s1   (cpu_data_master_read_data_valid_goIN_s1),
      .cpu_data_master_requests_goIN_s1          (cpu_data_master_requests_goIN_s1),
      .cpu_data_master_write                     (cpu_data_master_write),
      .d1_goIN_s1_end_xfer                       (d1_goIN_s1_end_xfer),
      .goIN_s1_address                           (goIN_s1_address),
      .goIN_s1_readdata                          (goIN_s1_readdata),
      .goIN_s1_readdata_from_sa                  (goIN_s1_readdata_from_sa),
      .goIN_s1_reset_n                           (goIN_s1_reset_n),
      .reset_n                                   (clk_reset_n)
    );

  goIN the_goIN
    (
      .address  (goIN_s1_address),
      .clk      (clk),
      .in_port  (in_port_to_the_goIN),
      .readdata (goIN_s1_readdata),
      .reset_n  (goIN_s1_reset_n)
    );

  goOUT_s1_arbitrator the_goOUT_s1
    (
      .clk                                        (clk),
      .cpu_data_master_address_to_slave           (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_goOUT_s1           (cpu_data_master_granted_goOUT_s1),
      .cpu_data_master_qualified_request_goOUT_s1 (cpu_data_master_qualified_request_goOUT_s1),
      .cpu_data_master_read                       (cpu_data_master_read),
      .cpu_data_master_read_data_valid_goOUT_s1   (cpu_data_master_read_data_valid_goOUT_s1),
      .cpu_data_master_requests_goOUT_s1          (cpu_data_master_requests_goOUT_s1),
      .cpu_data_master_waitrequest                (cpu_data_master_waitrequest),
      .cpu_data_master_write                      (cpu_data_master_write),
      .cpu_data_master_writedata                  (cpu_data_master_writedata),
      .d1_goOUT_s1_end_xfer                       (d1_goOUT_s1_end_xfer),
      .goOUT_s1_address                           (goOUT_s1_address),
      .goOUT_s1_chipselect                        (goOUT_s1_chipselect),
      .goOUT_s1_reset_n                           (goOUT_s1_reset_n),
      .goOUT_s1_write_n                           (goOUT_s1_write_n),
      .goOUT_s1_writedata                         (goOUT_s1_writedata),
      .reset_n                                    (clk_reset_n)
    );

  goOUT the_goOUT
    (
      .address    (goOUT_s1_address),
      .chipselect (goOUT_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_goOUT),
      .reset_n    (goOUT_s1_reset_n),
      .write_n    (goOUT_s1_write_n),
      .writedata  (goOUT_s1_writedata)
    );

  jtag_uart_avalon_jtag_slave_arbitrator the_jtag_uart_avalon_jtag_slave
    (
      .clk                                                           (clk),
      .cpu_data_master_address_to_slave                              (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_jtag_uart_avalon_jtag_slave           (cpu_data_master_granted_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave (cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_read                                          (cpu_data_master_read),
      .cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave   (cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_requests_jtag_uart_avalon_jtag_slave          (cpu_data_master_requests_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_waitrequest                                   (cpu_data_master_waitrequest),
      .cpu_data_master_write                                         (cpu_data_master_write),
      .cpu_data_master_writedata                                     (cpu_data_master_writedata),
      .d1_jtag_uart_avalon_jtag_slave_end_xfer                       (d1_jtag_uart_avalon_jtag_slave_end_xfer),
      .jtag_uart_avalon_jtag_slave_address                           (jtag_uart_avalon_jtag_slave_address),
      .jtag_uart_avalon_jtag_slave_chipselect                        (jtag_uart_avalon_jtag_slave_chipselect),
      .jtag_uart_avalon_jtag_slave_dataavailable                     (jtag_uart_avalon_jtag_slave_dataavailable),
      .jtag_uart_avalon_jtag_slave_dataavailable_from_sa             (jtag_uart_avalon_jtag_slave_dataavailable_from_sa),
      .jtag_uart_avalon_jtag_slave_irq                               (jtag_uart_avalon_jtag_slave_irq),
      .jtag_uart_avalon_jtag_slave_irq_from_sa                       (jtag_uart_avalon_jtag_slave_irq_from_sa),
      .jtag_uart_avalon_jtag_slave_read_n                            (jtag_uart_avalon_jtag_slave_read_n),
      .jtag_uart_avalon_jtag_slave_readdata                          (jtag_uart_avalon_jtag_slave_readdata),
      .jtag_uart_avalon_jtag_slave_readdata_from_sa                  (jtag_uart_avalon_jtag_slave_readdata_from_sa),
      .jtag_uart_avalon_jtag_slave_readyfordata                      (jtag_uart_avalon_jtag_slave_readyfordata),
      .jtag_uart_avalon_jtag_slave_readyfordata_from_sa              (jtag_uart_avalon_jtag_slave_readyfordata_from_sa),
      .jtag_uart_avalon_jtag_slave_reset_n                           (jtag_uart_avalon_jtag_slave_reset_n),
      .jtag_uart_avalon_jtag_slave_waitrequest                       (jtag_uart_avalon_jtag_slave_waitrequest),
      .jtag_uart_avalon_jtag_slave_waitrequest_from_sa               (jtag_uart_avalon_jtag_slave_waitrequest_from_sa),
      .jtag_uart_avalon_jtag_slave_write_n                           (jtag_uart_avalon_jtag_slave_write_n),
      .jtag_uart_avalon_jtag_slave_writedata                         (jtag_uart_avalon_jtag_slave_writedata),
      .reset_n                                                       (clk_reset_n)
    );

  jtag_uart the_jtag_uart
    (
      .av_address     (jtag_uart_avalon_jtag_slave_address),
      .av_chipselect  (jtag_uart_avalon_jtag_slave_chipselect),
      .av_irq         (jtag_uart_avalon_jtag_slave_irq),
      .av_read_n      (jtag_uart_avalon_jtag_slave_read_n),
      .av_readdata    (jtag_uart_avalon_jtag_slave_readdata),
      .av_waitrequest (jtag_uart_avalon_jtag_slave_waitrequest),
      .av_write_n     (jtag_uart_avalon_jtag_slave_write_n),
      .av_writedata   (jtag_uart_avalon_jtag_slave_writedata),
      .clk            (clk),
      .dataavailable  (jtag_uart_avalon_jtag_slave_dataavailable),
      .readyfordata   (jtag_uart_avalon_jtag_slave_readyfordata),
      .rst_n          (jtag_uart_avalon_jtag_slave_reset_n)
    );

  onchip_mem_s1_arbitrator the_onchip_mem_s1
    (
      .clk                                                      (clk),
      .cpu_data_master_address_to_slave                         (cpu_data_master_address_to_slave),
      .cpu_data_master_byteenable                               (cpu_data_master_byteenable),
      .cpu_data_master_byteenable_onchip_mem_s1                 (cpu_data_master_byteenable_onchip_mem_s1),
      .cpu_data_master_dbs_address                              (cpu_data_master_dbs_address),
      .cpu_data_master_dbs_write_16                             (cpu_data_master_dbs_write_16),
      .cpu_data_master_granted_onchip_mem_s1                    (cpu_data_master_granted_onchip_mem_s1),
      .cpu_data_master_no_byte_enables_and_last_term            (cpu_data_master_no_byte_enables_and_last_term),
      .cpu_data_master_qualified_request_onchip_mem_s1          (cpu_data_master_qualified_request_onchip_mem_s1),
      .cpu_data_master_read                                     (cpu_data_master_read),
      .cpu_data_master_read_data_valid_onchip_mem_s1            (cpu_data_master_read_data_valid_onchip_mem_s1),
      .cpu_data_master_requests_onchip_mem_s1                   (cpu_data_master_requests_onchip_mem_s1),
      .cpu_data_master_waitrequest                              (cpu_data_master_waitrequest),
      .cpu_data_master_write                                    (cpu_data_master_write),
      .cpu_instruction_master_address_to_slave                  (cpu_instruction_master_address_to_slave),
      .cpu_instruction_master_dbs_address                       (cpu_instruction_master_dbs_address),
      .cpu_instruction_master_granted_onchip_mem_s1             (cpu_instruction_master_granted_onchip_mem_s1),
      .cpu_instruction_master_latency_counter                   (cpu_instruction_master_latency_counter),
      .cpu_instruction_master_qualified_request_onchip_mem_s1   (cpu_instruction_master_qualified_request_onchip_mem_s1),
      .cpu_instruction_master_read                              (cpu_instruction_master_read),
      .cpu_instruction_master_read_data_valid_onchip_mem_s1     (cpu_instruction_master_read_data_valid_onchip_mem_s1),
      .cpu_instruction_master_requests_onchip_mem_s1            (cpu_instruction_master_requests_onchip_mem_s1),
      .d1_onchip_mem_s1_end_xfer                                (d1_onchip_mem_s1_end_xfer),
      .onchip_mem_s1_address                                    (onchip_mem_s1_address),
      .onchip_mem_s1_byteenable                                 (onchip_mem_s1_byteenable),
      .onchip_mem_s1_chipselect                                 (onchip_mem_s1_chipselect),
      .onchip_mem_s1_clken                                      (onchip_mem_s1_clken),
      .onchip_mem_s1_readdata                                   (onchip_mem_s1_readdata),
      .onchip_mem_s1_readdata_from_sa                           (onchip_mem_s1_readdata_from_sa),
      .onchip_mem_s1_write                                      (onchip_mem_s1_write),
      .onchip_mem_s1_writedata                                  (onchip_mem_s1_writedata),
      .registered_cpu_data_master_read_data_valid_onchip_mem_s1 (registered_cpu_data_master_read_data_valid_onchip_mem_s1),
      .reset_n                                                  (clk_reset_n)
    );

  onchip_mem the_onchip_mem
    (
      .address    (onchip_mem_s1_address),
      .byteenable (onchip_mem_s1_byteenable),
      .chipselect (onchip_mem_s1_chipselect),
      .clk        (clk),
      .clken      (onchip_mem_s1_clken),
      .readdata   (onchip_mem_s1_readdata),
      .write      (onchip_mem_s1_write),
      .writedata  (onchip_mem_s1_writedata)
    );

  //reset is asserted asynchronously and deasserted synchronously
  projection_reset_clk_domain_synch_module projection_reset_clk_domain_synch
    (
      .clk      (clk),
      .data_in  (1'b1),
      .data_out (clk_reset_n),
      .reset_n  (reset_n_sources)
    );

  //reset sources mux, which is an e_mux
  assign reset_n_sources = ~(~reset_n |
    0 |
    cpu_jtag_debug_module_resetrequest_from_sa |
    cpu_jtag_debug_module_resetrequest_from_sa);


endmodule


//synthesis translate_off



// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE

// AND HERE WILL BE PRESERVED </ALTERA_NOTE>


// If user logic components use Altsync_Ram with convert_hex2ver.dll,
// set USE_convert_hex2ver in the user comments section above

// `ifdef USE_convert_hex2ver
// `else
// `define NO_PLI 1
// `endif

`include "c:/altera/80/quartus/eda/sim_lib/altera_mf.v"
`include "c:/altera/80/quartus/eda/sim_lib/220model.v"
`include "c:/altera/80/quartus/eda/sim_lib/sgate.v"
`include "B4.v"
`include "B6.v"
`include "goOUT.v"
`include "jtag_uart.v"
`include "cpu_fpoint.v"
`include "B2.v"
`include "B8.v"
`include "B5.v"
`include "cpu_test_bench.v"
`include "cpu_mult_cell.v"
`include "cpu_jtag_debug_module_tck.v"
`include "cpu_jtag_debug_module_sysclk.v"
`include "cpu_jtag_debug_module_wrapper.v"
`include "cpu.v"
`include "B1.v"
`include "YOFF.v"
`include "XOFF.v"
`include "AREA.v"
`include "B7.v"
`include "onchip_mem.v"
`include "B3.v"
`include "RESET.v"
`include "goIN.v"

`timescale 1ns / 1ps

module test_bench 
;


  reg              clk;
  wire    [  4: 0] cpu_custom_instruction_master_multi_a;
  wire    [  4: 0] cpu_custom_instruction_master_multi_b;
  wire    [  4: 0] cpu_custom_instruction_master_multi_c;
  wire             cpu_custom_instruction_master_multi_estatus;
  wire    [ 31: 0] cpu_custom_instruction_master_multi_ipending;
  wire             cpu_custom_instruction_master_multi_readra;
  wire             cpu_custom_instruction_master_multi_readrb;
  wire             cpu_custom_instruction_master_multi_status;
  wire             cpu_custom_instruction_master_multi_writerc;
  wire    [ 31: 0] in_port_to_the_AREA;
  wire             in_port_to_the_RESET;
  wire    [  8: 0] in_port_to_the_XOFF;
  wire    [  8: 0] in_port_to_the_YOFF;
  wire             in_port_to_the_goIN;
  wire             jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
  wire             jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
  wire    [ 17: 0] out_port_from_the_B1;
  wire    [ 17: 0] out_port_from_the_B2;
  wire    [ 17: 0] out_port_from_the_B3;
  wire    [ 17: 0] out_port_from_the_B4;
  wire    [ 17: 0] out_port_from_the_B5;
  wire    [ 17: 0] out_port_from_the_B6;
  wire    [ 17: 0] out_port_from_the_B7;
  wire    [ 17: 0] out_port_from_the_B8;
  wire             out_port_from_the_goOUT;
  reg              reset_n;


// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
//  add your signals and additional architecture here
// AND HERE WILL BE PRESERVED </ALTERA_NOTE>

  //Set us up the Dut
  projection DUT
    (
      .clk                     (clk),
      .in_port_to_the_AREA     (in_port_to_the_AREA),
      .in_port_to_the_RESET    (in_port_to_the_RESET),
      .in_port_to_the_XOFF     (in_port_to_the_XOFF),
      .in_port_to_the_YOFF     (in_port_to_the_YOFF),
      .in_port_to_the_goIN     (in_port_to_the_goIN),
      .out_port_from_the_B1    (out_port_from_the_B1),
      .out_port_from_the_B2    (out_port_from_the_B2),
      .out_port_from_the_B3    (out_port_from_the_B3),
      .out_port_from_the_B4    (out_port_from_the_B4),
      .out_port_from_the_B5    (out_port_from_the_B5),
      .out_port_from_the_B6    (out_port_from_the_B6),
      .out_port_from_the_B7    (out_port_from_the_B7),
      .out_port_from_the_B8    (out_port_from_the_B8),
      .out_port_from_the_goOUT (out_port_from_the_goOUT),
      .reset_n                 (reset_n)
    );

  initial
    clk = 1'b0;
  always
    #10 clk <= ~clk;
  
  initial 
    begin
      reset_n <= 0;
      #200 reset_n <= 1;
    end

endmodule


//synthesis translate_on